DP159 Re-Initialization - 2.1 English

DisplayPort RX Subsystem LogiCORE IP Product Guide (PG233)

Document ID
PG233
Release Date
2023-05-25
Version
2.1 English

The PLL, RX, and TX settings of the DP159 must be re initialized while the DisplayPort Source is no longer detected. For example, on receiving the cable unplug interrupt event.

Table 1. DP159 Re-Initialization
Address Write/Read Data Description
0x00 Write 0x02 Disable PLL, clear A_LOCK_OVR
0x34 Write 0x01 Enable Offset Correction
0x02 Write 0x3F Set CP_CURRENT is high BW
0x01 Write 0x01 CP_EN is PLL mode
0x0B Write 0x33 PLL Loop filter 8K
0x4D Write 0x08 EQFTC = 0 and EQLEV = 8
0x4C Write 0x01 Set to Fixed EQ
0x33 Write 0xF0 Load Equalization settings
0x10 Write 0xF0 Disable all TX lanes
0x30 Write 0xE0 Enable RX Lane 0 only