Clocking - 2.1 English - PG233

This section describes the link clock (rx_lnk_clk), video clock (rx_vid_clk), and video bridge AXI4-Stream master interface clock. The rx_vid_clk should be 150 MHz or higher and the m_axis_aclk_stream<n> can be equal to or greater than the rx_vid_clk.

The DisplayPort RX Subsystem generates the rx_lnk_clk link clock input to the Video PHY (GT). The frequency of rx_lnk_clk is <line_rate>/40 MHz for the 32-bit video PHY (GT) data interface.

You must provide the hdcp_ext_clk in the 16-bit GT interface from external MMCM. The frequency requirement of hdcp_ext_clk is rx_lnk_clk/2.

The following table shows the clock ranges.

The core uses six clock domains:

lnk_clk

The rxoutclk from the Video PHY is connected to the RX subsystem link clock. Most of the core operates in link clock domain. This domain is based on the lnk_clk_p/n reference clock for the transceivers. The link rate switching is handled by a DRP state machine in the core PHY later. When the lanes are running at 2.7 Gb/s, lnk_clk operates at 135 MHz. When the lanes are running at 1.62 Gb/s, lnk_clk operates at 81 MHz. When the lanes are running at 5.4 Gb/s, lnk_clk operates at 270 MHz.

In the DisplayPort Sink core, lnk_clk is derived from the recovered clock from the transceiver. When the cable is disconnected this clock becomes unstable.

Note: lnk_clk = link_rate /20, when GT-Data width is 16-bit. lnk_clk = link_rate /40, when GT-Data width is 32-bit.

vid_clk

In MST mode, a single rx_vid_clk connects to all the stream video interfaces. This is the primary user interface clock. It is tested to run up to 200 MHz, which accommodates to a screen resolution of 2560x1600 when using two-wide pixels and larger when using the four-wide pixels. Based on the DisplayPort Standard , the video clock can be derived from the link clock using mvid and nvid. Also please make sure that the vid_clk frequency meets below requirement.

vid_clk >= (Vtotal * Htotal * fps) / Pixels per clock

s_axi_aclk

This is the processor domain. It is tested to run up to 135 MHz. The AUX clock domain is derived from this domain, but requires no additional constraints. In AMD UltraScale™ devices, s_axi_aclk clock is connected to a free-running clock input. The reset controller helper block requires the gtwiz_reset_clk_freerun_in signal to reset the transceiver primitives. A configuration parameter is added for AXI_Frequency, when the DisplayPort IP is targeted to UltraScale devices.

The requirement is s_axi_aclk ≤ lnk_clk.

aud_clk

This is the audio interface clock. The frequency is equal to 512 × audio sample rate.

s_aud_axis_aclk

The source audio streaming interface uses this clock. This clock should be = 512 × audio sample rate.

m_aud_axis_aclk

The sink audio streaming interface uses this clock. This clock should be = 512 × audio sample rate.

For more information on clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).