| Offset | R/W | Definition |
|---|---|---|
| 0x540 | RO |
MSA_HRES_STREAM2. The horizontal resolution detected in the Main Stream Attributes. [15:0] – Represents the number of pixels in a line of video. |
| 0x544 | RO |
MSA_HSPOL_STREAM2. Horizontal sync polarity. [0] – Indicates the polarity of the horizontal sync as requested by the transmitter. |
| 0x548 | RO |
MSA_HSWIDTH_STREAM2. Specifies the width of the horizontal sync pulse. [14:0] – Specifies the width of the horizontal sync in terms of the recovered video clock. |
| 0x54C | RO |
MSA_HSTART_STREAM2. This main stream attribute is the number of clock cycles between the leading edge of the horizontal sync and the first cycle of active data. [15:0] – Number of blanking cycles before active data. |
| 0x550 | RO |
MSA_HTOTAL_STREAM2. Tells the receiver core how many video clock cycles will occur between leading edges of the horizontal sync pulse. [15:0] – Total number of video clocks in a line of data. |
| 0x554 | RO |
MSA_VHEIGHT_STREAM2. Total number of active video lines in a frame of video. [15:0] – The vertical resolution of the received video. |
| 0x558 | RO |
MSA_VSPOL_STREAM2. Specifies the vertical sync polarity requested by the transmitter. [0] – A value of 1 in this register indicates an active-High vertical sync, and a 0 indicates an active-Low vertical sync. |
| 0x55C | RO |
MSA_VSWIDTH_STREAM2. The transmitter uses this value to specify the width of the vertical sync pulse in lines. [14:0] – Specifies the number of lines between the leading and trailing edges of the vertical sync pulse. |
| 0x560 | RO |
MSA_VSTART_STREAM2. This main stream attribute specifies the number of lines between the leading edge of the vertical sync pulse and the first line of active data. [15:0] – Number of blanking lines before the start of active data. |
| 0x564 | RO |
MSA_VTOTAL_STREAM2. Total number of lines between sequential leading edges of the vertical sync pulse. [15:0] – The total number of lines per video frame is contained in this value. |
| 0x568 | RO |
MSA_MISC0_STREAM2. Contains the value of the MISC0 attribute data. [7:5] – COLOR_DEPTH: Number of bits per color/component. [4] – YCbCR_COLOR: Set to 1 (ITU-R BT709-5) or 0 (ITU-R BT601-5). [3] – DYNAMIC_RANGE: Set to 1 (CEA range) or 0 (VESA range). [2:1] – COMPONENT_FORMAT: 00 = RGB 01 = YCbCr 4:2:2 10 = YCbCr 4:4:4 11 = Reserved [0] – CLOCK_MODE: 0 = Synchronous clock mode 1 = Asynchronous clock mode |
| 0x56C | RO |
MSA_MISC1_STREAM2. Contains the value of the MISC1 attribute data. [7] – Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. [6:3] – RESERVED: These bits are always set to 0. [2:1] – STEREO_VIDEO: Used only when stereo video sources are being transmitted. See the DisplayPort Standard v1.1a section 2.24 for more information. [0] – INTERLACED_EVEN: 1 indicates that the number of lines per frame is an even number. |
| 0x570 | RO |
MSA_MVID_STREAM2. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_NVID registers. [23:0] – MVID: Value of the clock recovery M value. |
| 0x574 | RO |
MSA_NVID_STREAM2. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_MVID registers. [23:0] – NVID: Value of the clock recovery N value. |
| 0x578 | RO |
MSA_VBID_STREAM2. The most recently received VB-ID value is contained in this register. [7:0] – VBID: See Table 2-3 (p44) in the DisplayPort Standard for more information. The default value is 0x19. |
| 0x580 | RO |
MSA_HRES_STREAM3. The horizontal resolution detected in the Main Stream Attributes. [15:0] – Represents the number of pixels in a line of video. |
| 0x584 | RO |
MSA_HSPOL_STREAM3. Horizontal sync polarity. [0] – Indicates the polarity of the horizontal sync as requested by the transmitter. |
| 0x588 | RO |
MSA_HSWIDTH_STREAM3. Specifies the width of the horizontal sync pulse. [14:0] – Specifies the width of the horizontal sync in terms of the recovered video clock. |
| 0x59C | RO |
MSA_HSTART_STREAM3. This main stream attribute is the number of clock cycles between the leading edge of the horizontal sync and the first cycle of active data. [15:0] – Number of blanking cycles before active data. |
| 0x590 | RO |
MSA_HTOTAL_STREAM3. Tells the receiver core how many video clock cycles will occur between leading edges of the horizontal sync pulse. [15:0] – Total number of video clocks in a line of data. |
| 0x594 | RO |
MSA_VHEIGHT_STREAM3. Total number of active video lines in a frame of video. [15:0] – The vertical resolution of the received video. |
| 0x598 | RO |
MSA_VSPOL_STREAM3. Specifies the vertical sync polarity requested by the transmitter. [0] – A value of 1 in this register indicates an active-High vertical sync, and a '0' indicates an active-Low vertical sync. |
| 0x59C | RO |
MSA_VSWIDTH_STREAM3. The transmitter uses this value to specify the width of the vertical sync pulse in lines. [14:0] – Specifies the number of lines between the leading and trailing edges of the vertical sync pulse. |
| 0x5A0 | RO |
MSA_VSTART_STREAM3. This main stream attribute specifies the number of lines between the leading edge of the vertical sync pulse and the first line of active data. [15:0] – Number of blanking lines before the start of active data. |
| 0x5A4 | RO |
MSA_VTOTAL_STREAM3. Total number of lines between sequential leading edges of the vertical sync pulse. [15:0] – The total number of lines per video frame is contained in this value. |
| 0x5A8 | RO |
MSA_MISC0_STREAM3. Contains the value of the MISC0 attribute data. [7:5] – COLOR_DEPTH: Number of bits per color/component. [4] – YCbCR_COLOR: Set to 1 (ITU-R BT709-5) or 0 (ITU-R BT601-5). [3] – DYNAMIC_RANGE: Set to 1 (CEA range) or 0 (VESA range). [2:1] – COMPONENT_FORMAT: 00 = RGB 01 = YCbCr 4:2:2 10 = YCbCr 4:4:4 11 = Reserved [0] – CLOCK_MODE: 0 = Synchronous clock mode 1 = Asynchronous clock mode |
| 0x5AC | RO |
MSA_MISC1_STREAM3. Contains the value of the MISC1 attribute data. [7] – Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. [6:3] – RESERVED: These bits are always set to 0. [2:1] – STEREO_VIDEO: Used only when stereo video sources are being transmitted. See the DisplayPort Standard v1.1a section 2.24 for more information. [0] – INTERLACED_EVEN: 1 indicates that the number of lines per frame is an even number. |
| 0x5B0 | RO |
MSA_MVID_STREAM3. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_NVID registers. [23:0] – MVID: Value of the clock recovery M value. |
| 0x5B4 | RO |
MSA_NVID_STREAM3. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_MVID registers. [23:0] – NVID: Value of the clock recovery N value. |
| 0x5B8 | RO |
MSA_VBID_STREAM3. The most recently received VB-ID value is contained in this register. [7:0] – VBID: See Table 2-3 (p44) in the DisplayPort Standard for more information. The default value is 0x19. |
| 0x5C0 | RO |
MSA_HRES_STREAM4. The horizontal resolution detected in the Main Stream Attributes. [15:0] – Represents the number of pixels in a line of video. |
| 0x5C4 | RO |
MSA_HSPOL_STREAM4. Horizontal sync polarity. [0] – Indicates the polarity of the horizontal sync as requested by the transmitter. |
| 0x5C8 | RO |
MSA_HSWIDTH_STREAM4. Specifies the width of the horizontal sync pulse. [14:0] – Specifies the width of the horizontal sync in terms of the recovered video clock. |
| 0x5CC | RO |
MSA_HSTART_STREAM4. This main stream attribute is the number of clock cycles between the leading edge of the horizontal sync and the first cycle of active data. [15:0] – Number of blanking cycles before active data. |
| 0x5D0 | RO |
MSA_HTOTAL_STREAM4. Tells the receiver core how many video clock cycles will occur between leading edges of the horizontal sync pulse. [15:0] – Total number of video clocks in a line of data. |
| 0x5D4 | RO |
MSA_VHEIGHT_STREAM4. Total number of active video lines in a frame of video. [15:0] – The vertical resolution of the received video. |
| 0x5D8 | RO |
MSA_VSPOL_STREAM4. Specifies the vertical sync polarity requested by the transmitter. [0] – A value of 1 in this register indicates an active-High vertical sync, and a '0' indicates an active-Low vertical sync. |
| 0x5DC | RO |
MSA_VSWIDTH_STREAM4. The transmitter uses this value to specify the width of the vertical sync pulse in lines. [14:0] – Specifies the number of lines between the leading and trailing edges of the vertical sync pulse. |
| 0x5E0 | RO |
MSA_VSTART_STREAM4. This main stream attribute specifies the number of lines between the leading edge of the vertical sync pulse and the first line of active data. [15:0] – Number of blanking lines before the start of active data. |
| 0x5E4 | RO |
MSA_VTOTAL_STREAM4. Total number of lines between sequential leading edges of the vertical sync pulse. [15:0] – The total number of lines per video frame is contained in this value. |
| 0x5E8 | RO |
MSA_MISC0_STREAM4. Contains the value of the MISC0 attribute data. [7:5] – COLOR_DEPTH: Number of bits per color/component. [4] – YCbCR_COLOR: Set to 1 (ITU-R BT709-5) or 0 (ITU-R BT601-5). [3] – DYNAMIC_RANGE: Set to 1 (CEA range) or 0 (VESA range). [2:1] – COMPONENT_FORMAT: 00 = RGB 01 = YCbCr 4:2:2 10 = YCbCr 4:4:4 11 = Reserved [0] – CLOCK_MODE: 0 = Synchronous clock mode 1 = Asynchronous clock mode |
| 0x5EC | RO |
MSA_MISC1_STREAM4. Contains the value of the MISC1 attribute data. [7] – Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. [6:3] – RESERVED: These bits are always set to 0. [2:1] – STEREO_VIDEO: Used only when stereo video sources are being transmitted. See the DisplayPort Standard v1.1a section 2.24 for more information. [0] – INTERLACED_EVEN: 1 indicates that the number of lines per frame is an even number. |
| 0x5F0 | RO |
MSA_MVID_STREAM4. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_NVID registers. [23:0] – MVID: Value of the clock recovery M value. |
| 0x5F4 | RO |
MSA_NVID_STREAM4. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_MVID registers. [23:0] – NVID: Value of the clock recovery N value. |
| 0x5F8 | RO |
MSA_VBID_STREAM4. The most recently received VB-ID value is contained in this register. [7:0] – VBID: See Table 2-3 (p44) in the DisplayPort Standard for more information. The default value is 0x19. |
| 0xA00 to 0xAFF | RO | DOWN_REQUEST_BUFFER. Down Request Buffer address space. User has to read sideband message request from the address 0xA00 – 0xA30. The rest of the address space is reserved. |
| 0xB00 to 0xBFF | WO | DOWN_REPLY_BUFFER. Down Reply Buffer address space. User has to write sideband message reply in the address starting from 0xB00 for every new reply. Reply Buffer can handle up to 32 bytes. The rest of the address space is reserved. |
| 0xC00 to 0xCFF | RO | UPSTREAM_REQUEST_BUFFER. Reserved. |
| 0xD00 to 0xDFF | WO | UPSTREAM_REPLY_BUFFER. Reserved. |
| 0x800 to 0x8FF | RW | PAYLOAD_TABLE. This address space maps to the VC Payload table that is maintained in the core. Write access is provided when VCPayload table is in software control. |