| Offset | R/W | Definition |
|---|---|---|
| 0x208 | RO |
PHY_STATUS. Provides status for the receiver core PHY. [31:30] – RX buffer status, lane 3. [29:28] – RX buffer status, lane 2. [27:26] – RX buffer status, lane 1. [25:24] – RX buffer status, lane 0. [23] – RXBYTEISALIGNED status of PHY, lane 3. [22] – RXBYTEISALIGNED status of PHY, lane 2. [21] – RXBYTEISALIGNED status of PHY, lane 1. [20] – RXBYTEISALIGNED status of PHY, lane 0. [15:14] – RX voltage low, lanes 2 and 3. [13:12] – RX voltage low, lanes 0 and 1. [11:10] – PRBS error, lanes 2 and 3. [9:8] – PRBS error, lanes 0 and 1. [7] – Receiver Clock locked. [6] – FPGA fabric clock PLL locked. [5] – PLL for lanes 2 and 3 locked (Tile 1). [4] – PLL for lanes 0 and 1 locked (Tile 0). [3:2] – Reset done for lanes 2 and 3 (Tile 1). [1:0] – Reset done for lanes 0 and 1 (Tile 0). |
| 0x214 | RW |
MIN_VOLTAGE_SWING. Some DisplayPort implementations require the transmitter to set a minimum voltage swing during training before the link can be reliably established. This register is used to set a minimum value which must be met in the TRAINING_LANEX_SET DPCD registers. The internal training logic will force training to fail until this value is met. It is not recommended to change this register value.[23:14] – PREEMP_TABLE (only for Advanced users). 15:14: Iteration 1 pre-emp request level 17:16: Iteration 2 pre-emp request level 19:18: Iteration 3 pre-emp request level 21:20: Iteration 4 pre-emp request level 23:22: Iteration 5 pre-emp request level [13:12] – SET_PREEMP (only for Advanced users). [11:10] – Channel Equalization options (only for Advanced users). 00: Default (pre-emphasis adjust request will get incremented one by per iteration until maximum pre-emphasis limit (SET_PREEMP) is reached) 01: Hold pre-emphasis adjust request to SET_PREEMP for all iterations 10: Not applicable 11: Pick values from PREEMP_TABLE [9:8] – SET_VSWING (only for Advanced users). Default value is 0x0000. [6:4] – VSWING_SWEEP_CNT (only for Advanced users). [3:2] – Clock Recovery options (only for Advanced users). 00: Default (Voltage swing adjust request will get incremented one by every iteration) 01: Increment adjust request every 4 or VSWING_SWEEP_CNT iterations 10: Hold adjust request to SET_VSWING value for all iterations 11: Not applicable [1:0] – The minimum voltage swing setting matches the values defined in the DisplayPort Standard for the TRAINING_LANEX_SET register. |
| 0x21C | RW |
CDR_CONTROL_CONFIG. [30] – Disable Training Timeout. [19:0] – Controls the CDR tDLOCK timeout value. The counter is run using the AXI4-Lite clock in the PHY Module. Default value is 20'h1388. |
| 0x220 | RW |
BS_IDLE_TIME. Blanking start symbol idle time. Default is 0x1312D00 (200 ms) considering 100 MHz AXI4-Lite clock frequency. The value is based on AXI4-Lite clock frequency and you are expected to update as needed. [31:0] – The value written in this register is used in the DisplayPort Sink to detect cable disconnect or unplug event. The DisplayPort sink checks the Blanking Start symbol over the link for the specified period and generates cable unplug interrupt. The timeout counter is loaded with this register value which is working with AXI clock. The cable unplug counter is a free running counter and it reloads with BS_IDLE_TIME as and when it receives the BS character over the link or when it times out by reaching maximum count. |