The GPU must inform the sink of the link bandwidth (LINK_BW_SET) and the number of lanes (LANE_COUNT_SET) before beginning the link training. At this stage, the software must program the PLL enable and number of RX lanes of DP159. When PLL lock has been achieved, the software must immediately transition the PLL mode of operation from PLL_MODE to PD_MODE. It is also important to enable the TX lanes, at this stage, so that the DisplayPort sink can start performing the clock recovery.
| Address | Read/Write | Data | Description |
|---|---|---|---|
| Bandwidth and Number of Lanes | |||
| 0x00 | Write | 0x02 | Enable Bandgap, DISABLE PLL, clear A_LOCK_OVR |
| 0x01 | Write | 0x01 | CP_EN = PLL (reference) mode |
| 0x0B | Write | 0x33 | Set PLL control |
| 0x02 | Write | 0x3F | Set CP_CURRENT |
| 0x30 | Write |
0xE1 0xC3 0x0F |
Set RX Lane count Lane count 1 Lane count2 Lanecount4 |
| 0x00 | Write | 0x03 | Enable Bandgap, Enable PLL, clear A_LOCK_OVR |
| 0x4C | Write | 0x01 | Enable fixed EQ |
| 0x4D | Write |
0x08 0x18 0x28 |
Set EQFTC and EQLEV (fixed EQ) HBR2 HBR RBR |
| 0x10 | Write |
0xE1 0xC3 0x0F |
Enable TX lanes Lane count 1 Lane count2 Lanecount4 |
| 0x00 | Write | 0x23 | Enable PLL and Bandgap, set A_LOCK_OVR |
| Determine the PLL lock of DP159. If achieved, change PLL mode based on the lane rate. Continue programming, after the DP159 PLL lock. | |||
| 0x02 | Write |
0x5F 0x27 0x1F |
CP_CURRENT HBR2 HBR RBR |
| 0x0B | Write | 0x30 | PLL loop filter 1K |
| 0x01 | Write | 0x02 | CP_EN is PD mode |
| 0xFF | Write | 0x00 | Select Page0 |
| 0x16 | Write |
0x11 0x31 0xF1 0xF1 |
Set DP_TST_EN per #lanes, latch FIFO errors Lane Count1 Lane count 2 Lane count4 Set DP_TST_EN on all lanes to disable char-alignment |
| 0x10 | Write | 0x00 | Disable PV |
| 0xFF | Write | 0x01 | Select Page1 |