The following registers must be programmed immediately after power-up to configure the DP159 PLL, TX and RX blocks.
| IIC Address | Write/Read | Data | Description |
|---|---|---|---|
| 0xFF | Write | 0x00 | Select Page 0 |
| 0x09 | Write | 0x36 | Enable X-mode |
| 0x0A | Write | 0x7B | Disable HPD_SNK pass-through to HPD_SRC. |
| 0x0D | Write | 0x80 | Enable Clock on AUX. Select 1/20 mode. |
| 0x0C | Write | 0x6D | Set TX Swing to Maximum |
| 0x10 | Write | 0x00 | Turn off pattern verifier |
| 0x11 | Len = PRBS23, Sel = PRBS mode to turn off char-alignment | ||
| 0x16 | Write | 0xF1 | Disable char-alignment on all lanes |
| 0xFF | Write | 0x01 | Select Page 1 |
| Configure PLL | |||
| 0x00 | Write | 0x02 | Enable Band Gap |
| 0x04 | Write | 0x80 | PLL_FBDIV[7:0] |
| 0x05 | Write | 0x00 | PLL_FBDIV[10:8] |
| 0x08 | Write | 0x00 | PLL_PREDIV[7:0] |
| 0x0D | Write | 0x02 | Selects Lane0 for clock |
| 0x0E | Write | 0x03 | CDR_CONFIG [4:0]. FIXED, LN0 |
| 0x01 | Write | 0x01 | CP_EN is PLL mode |
| 0x02 | Write | 0x3F | CP_Current is High |
| 0x0B | Write | 0x33 | Loop filter to 8K |
| 0xA1 | Write | 0x02 | Override PLL settings |
| 0xA4 | Write | 0x02 | Override PLL settings |
| Configure TX Block | |||
| 0x10 | Write | 0xF0 | Disable for all four TX lanes |
| 0x11 | Write | 0x30 | TX_RATE is Full Rate, TX_TERM = 75 to 150, TX_INVPAIR = None |
| 0x14 | Write | 0x00 | HDMI_TWPST1 is 0 dB de-emphasis |
| 0x12 | Write | 0x03 | SLEW_CTRL is Normal, SWING is 600 mV. |
| 0x13 | Write | 0xFF | FIR_UPD. Load TX settings |
| 0x13 | Write | 0x00 | |
| Configure RX Block | |||
| 0x30 | Write | 0XE0 | Disable Receivers except lane0 |
| 0x32 | Write | 0x00 | PD_RXINT |
| 0x31 | Write | 0x00 | RX_Rate is full |
| 0x4D | Write | 0x08 | EQFTC = 0 and EQLEV = 8 |
| 0x4C | Write | 0x01 | Enable Fixed EQ |
| 0x34 | Write | 0x01 | Enable Offset Correction |
| 0x32 | Write | 0xF0 | Load RX settings |
| 0x32 | Write | 0X00 | |
| 0x33 | Write | 0xF0 | Load EQ settings. |
| 0xFF | Write | 0x00 | Select Page0 |
| 0x0A | Write | 0X3B | Enable HPD_SNK pass thru to HPD_SRC. Retimer |
| 0xFF | Write | 0x01 | Select Page1 |