| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
AMD UltraScale+™
Families
(GTHE4) AMD UltraScale™ Families (GTHE3) AMD Zynq™ 7000 SoC (GTXE2) AMD Virtex™ 7 (GTXE2) and AMD Kintex™ 7 (GTXE2) |
| Supported User Interfaces | AXI4-Lite, AXI4-Stream, Native video |
| Resources | Performance and Resource Utilization web page |
| Provided with Subsystem | |
| Design Files | Hierarchical subsystem packaged with DisplayPort RX core and other IP cores |
| Example Design | AMD Vivado™ IP integrator |
| Test Bench | N/A |
| Constraints File | IP cores delivered with XDC files |
| Simulation Model | N/A |
| Supported S/W Driver | Standalone |
| Tested Design Flows 3 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation and Licensing. |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 65447 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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