Register Space - 2.1 English

This section details registers available in the DisplayPort RX Subsystem. The address map is split into following regions:

• DisplayPort Receive (RX) IP
• AXI IIC
• HDCP
• AXI Timer

The subsystem address propagation in the AMD Vivado™ IP integrator assigns the maximum addresses based on full featured configuration. Ensure the following steps are taken:

1. Confirm that the DisplayPort RX subsystem IP is mapped to a base address where the 14^th bit in the address is 0. For example, 0x44A00000 is correct and 0x44A02000 causes errors.
2. Ensure that all 14 bits of the address range are reserved for the DisplayPort RX subsystem IP.

The DisplayPort Configuration Data is implemented as a set of distributed registers which can be read or written from the AXI4-Lite interface. These registers are considered to be synchronous to the AXI4-Lite domain and asynchronous to all others.

For parameters that might change while being read from the configuration space, two scenarios might exist. In the case of single bits, either the new value or the old value is read as valid data. In the case of multiple bit fields, a lock bit might be maintained to prevent the status values from being updated while the read is occurring. For multi-bit configuration data, a toggle bit is used indicating that the local values in the functional core should be updated.

Any bits not specified in Receiver Core Configuration to Vendor-Specific DPCD are to be considered reserved and returns 0 upon read. Only address offsets are listed in these register tables; base addresses are configured by the AXI Interconnect.