DPCD Configuration Space - 2.1 English

DPCD_LINK_BW_SET. Link bandwidth setting.

[7:0] – Set to 0x0A when the link is configured for 2.7 Gb/s or 0x06 when configured for 1.62 Gb/s or 0x14 when link is configured for 5.4 Gb/s.

DPCD_LANE_COUNT_SET. Number of lanes enabled by the transmitter.

[4:0] – Contains the number of lanes that are currently enabled by the attached transmitter. Valid values fall in the range of 1-4.

DPCD_ENHANCED_FRAME_EN. Indicates that the transmitter has enabled the enhanced framing symbol mode.

[0] – Set to 1 when enhanced framing mode is enabled.

DPCD_TRAINING_PATTERN_SET. Current value of the training pattern registers.

[1:0] – TRAINING_PATTERN_SET: Set the link training pattern according to the two bit code:

00 = Training not in progress

01 = Training pattern 1

10 = Training pattern 2

11 = RESERVED

DPCD_LINK_QUALITY_PATTERN_SET. Current value of the link quality pattern field of the DPCD training pattern register.

[1:0] – transmitter is sending the link quality pattern:

00 = Link quality test pattern not transmitted

01 = D10.2 test pattern (unscrambled) transmitted

10 = Symbol Error Rate measurement pattern

11 = PRBS7 transmitted

DPCD_RECOVERED_CLOCK_OUT_EN. Value of the output clock enable field of the DPCD training pattern register.

[0] – Set to 1 to output the recovered receiver clock on the test port.

DPCD_SCRAMBLING_DISABLE. Value of the scrambling disable field of the DPCD training pattern register. By default, scrambling is disabled.

[0] – Set to 1 when the transmitter has disabled the scrambler and transmits all symbols.

DPCD_SYMBOL_ERROR_COUNT_SELECT. Current value of the symbol error count select field of the DPCD training pattern register.

[1:0] – SYMBOL_ERROR_COUNT_SEL:

00 = Disparity error and illegal symbol error

01 = Disparity error

10 = Illegal symbol error

11 = Reserved

DPCD_TRAINING_LANE_0_SET. Used by the transmitter during link training to configure the receiver PHY for lane 0.

[5] – MAX_PRE-EMPHASIS_REACHED: Set to 1 when the maximum pre-emphasis setting is reached.

[4:3] – PRE-EMPHASIS_SET

00 = Training Pattern 2 without pre-emphasis

01 = Training Pattern 2 with pre-emphasis level 1

10 = Training Pattern 2 with pre-emphasis level 2

11 = Training Pattern 2 with pre-emphasis level 3

[2] – MAX_SWING_REACHED: Set to '1' when the maximum driven current setting is reached.

[1:0] – VOLTAGE_SWING_SET

00 = Training Pattern 1 with voltage swing level 0

01 = Training Pattern 1 with voltage swing level 1

10 = Training Pattern 1 with voltage swing level 2

11 = Training Pattern 1 with voltage swing level 3

DPCD_DOWNSPREAD_CONTROL. The transmitter uses this bit to inform the receiver core that down-spreading has been enabled.

[0] – SPREAD_AMP: Set to 1 for 0.5% spreading or 0 for none.

DPCD_MAIN_LINK_CHANNEL_CODING_SET. 8B/10B encoding can be disabled by the transmitter through this register bit.

[0] – Set to 0 to disable 8B/10B channel coding. The default is 1.

DPCD_SET_POWER_STATE. Power state requested by the source core. On reset, power state is set to power down mode.

[1:0] – requested power state

00 = Reserved

01 = state D0, normal operation

10 = state D3, power down mode

11 = Reserved

DPCD_LANE01_STATUS. Value of the lane 0 and lane 1 training status registers.

[6] – LANE_1_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_1.

[5] – LANE_1_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_1.

[4] – LANE_1_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_1.

[2] – LANE_0_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_0.

[1] – LANE_0_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_0.

[0] – LANE_0_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_0.

DPCD_LANE23_STATUS. Value of the lane 2 and lane 3 training status registers.

[6] – LANE_3_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_3.

[5] – LANE_3_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_3.

[4] – LANE_3_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_3.

[2] – LANE_2_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_2.

[1] – LANE_2_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_2.

[0] – LANE_2_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_2.

SOURCE_OUI_VALUE. Value of the Organizationally Unique Identifier (OUI) as written by the transmitter via the DPCD register AUX transaction.

[23:0] – Contains the value of the OUI set by the transmitter. This value might be used by the host policy maker to enable special functions across the link.

SYM_ERR_CNT01. Reports symbol error counter of lanes 0 and 1. The lane 0 and lane 1 error counts are cleared when this register is read.

[31] = Lane 1 error count valid.

[30:16] = Lane 1 error count.

[15] = Lane 0 error count valid.

[14:0] = Lane 0 error count.

SYM_ERR_CNT23. Reports symbol error counter of lanes 2 and 3. The lane 2 and lane 3 error counts are cleared when this register is read.

[31] = Lane 3 error count valid.

[30:16] = Lane 3 error count.

[15] = Lane 2 error count valid.

[14:0] = Lane 2 error count.