Receive – FIFO Overflow - 2.1 English

DisplayPort RX Subsystem LogiCORE IP Product Guide (PG233)

Document ID
PG233
Release Date
2023-05-25
Version
2.1 English

How do I resolve the USER_FIFO_OVERFLOW interrupts (0x110) when I am using the DisplayPort in Receiver mode?

This is caused when the outgoing data stream on the rx_vid_clk domain is not fast enough compared to the incoming Display Port data stream on the lnk_clk domain.

This causes the DisplayPort data stream to get pushed into the FIFO faster than the speed the FIFO can be read out.

There are two ways to resolve this:

  1. If possible, increase HBLANK from the source.
  2. Increase the rx_vid_clk frequency to the maximum tested of 200 MHz.
Note: FIFO overflow can be due to a backpressure on the DisplayPort IP. You must make sure that the TREADY signals are tied to “1”. When enabling SDP for HDR mode without using the audio channel, the AUD_AXI_EGRESS_TVALID signal should be tied to “1”.