Receive – Training - 2.1 English

This section contains debugging steps if the clock recovery or channel equalization is not happening at sink.

• Try with a different source such as the DisplayPort Analyzer.
• Change the cable and check again.
• Put an AUX Analyzer in the receive path and check if the various training stages match with the one's mentioned in DisplayPort Overview.
• Probe the lnk_clk output and check the SI of the Clock is within the Phase Noise mask of the respective GT Transceiver.
• Check the RX Initialization Status register (0x0028) and PLL Lock Status (0x0018) register of the Video PHY Controller for Reset done and PLL lock for the active lanes.
• Check the 0x43C and 0x440 registers for Symbol_Locked, Channel Equalization, and Clock Recovery Done.