Constraining the Core - 2.1 English

DisplayPort RX Subsystem LogiCORE IP Product Guide (PG233)

Document ID
PG233
Release Date
2023-05-25
Version
2.1 English

Required Constraints

There are no required constraints for this core. Being a subsystem, all sub-cores generate their own constraints and the same is applied in the subsystem.

Device, Package, and Speed Grade Selections

See Features for details about supported devices.

Clock Frequencies

See Clocking for more details about clock frequencies.

Clock Management

There are no specific clock management constraints.

Clock Placement

There are no specific clock placement constraints.

Banking

For more information on the specific banking constraints, see the Video PHY Controller LogiCORE IP Product Guide (PG230).

Transceiver Placement

Transceiver is external to DisplayPort RX Subsystem hence there are no specific transceiver placement constraints. For more information on the specific transceiver placement constraints, see the Video PHY Controller LogiCORE IP Product Guide (PG230).