The primary interface for user image data has been modeled on the industry standard for display timing controller signals. The port list consists of video timing information encoded in a vertical and horizontal sync pulse and data valid indicator. These single-bit control lines frame the active data and provide flow control for the AXI4-Stream video.
Vertical timing is framed using the vertical sync pulse, which indicates the end of frame N-1 and the beginning of frame N. The vertical back porch is defined as the number of horizontal sync pulses between the end of the vertical sync pulse and the first line containing active pixel data. The vertical front porch is defined as the number of horizontal sync pulses between the last line of active pixel data and the start of the vertical sync pulse. When combined with the vertical back porch and the vertical sync pulse width, these parameters form what is commonly known as the vertical blanking interval.
At the trailing edge of each vertical sync pulse, the user data interface resets the key elements of the image datapath. This provides for a robust user interface that recovers from any kind of interface error in one vertical interval or less.
You have the option to use the resolved M and N values from the stream to generate a clock, or to use a sufficiently-fast clock and pipe the data into a line buffer. AMD recommends using a fast clock and ignoring the M and N values unless you can be certain of the source of these values. Unlike the Source core, when using a fast clock, the data valid signal might toggle within a scan line. The following figure shows the typical signaling of a full frame of data.
The horizontal timing information is defined by a front porch, back porch, and pulse width. The porch values are defined as the number of clocks between the horizontal sync pulse and the start or end of active data. Pixel data is only accepted into the image data interface when the data valid flag is active-High. The following figure is an enlarged version of the previous figure, giving more detail on a single scan line.
The horizontal sync pulse should be used as a line advance signal. Use the rising edge of this signal to increment the line count.
Data
Valid might toggle if using a fast clock.
In the two-dimensional image plane, these control signals frame a rectangular region of active pixel data within the total frame size. This relationship of the total frame size to the active frame size is shown in the following figure.
The User Data Interface can accept one, two, or four pixels per clock cycle. The second pixel is active only when USER_PIXEL_WIDTH is set and the negotiated number of lanes is greater than one.
The vid_pixel width is always 48-bits,
regardless of if all bits are used. For pixel mappings that do not require all 48-bits,
the convention used for this core is to occupy the MSB bits first and leave the lower
bits either untied or driven to zero. The following table provides the mapping for all
supported data formats.
| Format | BPC/BPP | R | G | B | Cr | Y | Cb | Cr/Cb | Y |
|---|---|---|---|---|---|---|---|---|---|
| RGB | 6/18 | [47:42] | [31:26] | [15:10] | – | – | – | – | – |
| RGB | 8/24 | [47:40] | [31:24] | [15:8] | – | – | – | – | – |
| RGB | 10/30 | [47:38] | [31:22] | [15:6] | – | – | – | – | – |
| RGB | 12/36 | [47:36] | [31:20] | [15:4] | – | – | – | – | – |
| RGB | 16/48 | [47:32] | [31:16] | [15:0] | – | – | – | – | – |
| YCbCr444 | 6/18 | – | – | – | [47:42] | [31:26] | [15:10] | – | – |
| YCbCr444 | 8/24 | – | – | – | [47:40] | [31:24] | [15:8] | – | – |
| YCbCr444 | 10/30 | – | – | – | [47:38] | [31:22] | [15:6] | – | – |
| YCbCr444 | 12/36 | – | – | – | [47:36] | [31:20] | [15:4] | – | – |
| YCbCr444 | 16/48 | – | – | – | [47:32] | [31:16] | [15:0] | – | – |
| YCbCr422 | 8/16 | – | – | – | – | – | – | [47:40] | [31:24] |
| YCbCr422 | 10/20 | – | – | – | – | – | – | [47:38] | [31:22] |
| YCbCr422 | 12/24 | – | – | – | – | – | – | [47:36] | [31:20] |
| YCbCr422 | 16/32 | – | – | – | – | – | – | [47:32] | [31:16] |
| YONLY | 8/8 | – | – | – | – | – | – | – | [47:40] |
| YONLY | 10/10 | – | – | – | – | – | – | – | [47:38] |
| YONLY | 12/12 | – | – | – | – | – | – | – | [47:36] |
| YONLY | 16/16 | – | – | – | – | – | – | – | [47:32] |
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The design allows use of a faster pixel clock, for example, 150 MHz or higher video clock frequency for all standard video resolutions. The DisplayPort RX supports DMA mode without any internal line buffers for video display. You need to reproduce the exact video timing from the M_vid and N_vid values reported in the Main Stream Attribute (MSA) data. The interface timing in this case is shown in the following figure.
rx_vid_vsync, rx_vid_hsync, rx_vid_enable and the
number of hsync pulses shown in the previous figure are scaled down to have better
visibility. The number of hsync pulses are equal to the number of active lines in a
frame. The default widths of rx_vid_hsync pulse is 16
and rx_vid_vsync pulse is 63. The widths hsync and
vsync can be controlled through software as per the MSA.