AXI4-Lite Interface Ports - 2.1 English

DisplayPort RX Subsystem LogiCORE IP Product Guide (PG233)
Document ID
PG233
Release Date
2023-05-25
Version
2.1 English
Table 1. AXI4-Lite Interface Ports
Signal Name I/O Description
s_axi_aclk I AXI bus clock
s_axi_aresetn I AXI reset. Active-Low.
s_axi_awaddr[13:0] I Write address
s_axi_awprot[2:0] I Protection type
s_axi_awvalid I Write address valid
s_axi_awready O Write address ready
s_axi_wdata[31:0] I Write data
s_axi_wstrb[3:0] I Write strobe
s_axi_wvalid I Write data valid
s_axi_wready O Write data ready
s_axi_bresp[1:0] O Write response
s_axi_bvalid O Write response valid
s_axi_bready I Write response ready
s_axi_araddr[13:0] I Read address
s_axi_arprot[2:0] I Read protection type
s_axi_arvalid I Read address valid
s_axi_arready O Read address ready
s_axi_rdata[31:0] O Read data
s_axi_rresp[1:0] O Read data response
s_axi_rvalid O Read data valid
s_axi_rready I Read data ready