User Parameters - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

Document ID
PG238
Release Date
2023-10-18
Version
2.3 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Vivado IDE Parameter User Parameter Default Value Allowable Value
DSI_LANES DSI Lanes 1 to 4 Maximum of four lanes
DSI_DATATYPE DSI Data type RGB888

RGB666 (Loosely, Packed), RGB565, RGB888,

Compressed Pixel stream.

(Only formats listed in sec 10.2.1 of DSI Specification are supported.)

DSI_CRC_GEN CRC Generation logic 1

0: No CRC calculated for long packets, fixed to 0x0000

1: CRC calculated for long packets

C_DSI_XMIT_INITIAL_DESKEW

Enable Initial Deskew

Transmission

0

0: No initial skew calibration packets sent.

1: the core generates initial skew calibration packets.

C_INCLUDE_DCS_CMD_MODE DCS Command Mode, 0

0: The subsystem does not support command only mode and long command packets.

1: Supports long and short commands in command mode.

DSI_PIXELS Input Pixels per beat 1

Pixels per beat received on input stream interface

Single pixel per beat

Dual pixels per beat Quad pixels per beat

DHY_LINERATE Line Rate (Mbps) 800

Versal Adaptive SoCs: 260–2500 Mbps

UltraScale+ /7 series: 80–2500 Mbps

DPHY_LPX_PERIOD LPX Period (ns) 50 50–100 (ns)
C_EN_CTS_TX Guarantees the rising edge clock alignment to first payload data bit False

True: Guarantees the rising edge clock alignment to first payload data bit.

False: Do not guarantee the rising edge clock alignment to first payload data bit.

Note: Applicable only for Versal devices.
DPHY_EN_REGIF Enable AXI4-Lite Register I/F 0

0: Disable register interface for DPHY

1: Enable register interface for DPHY

SupportLevel Shared Logic 0  
HP_IO_BANK_SELECTION HP IO Bank Selection Value based on part selected.
CLK_LANE_IO_LOC Clock Lane Value based on part selected.
DATA_LANE0_IO_LOC Data Lane0 Value based on part selected.
DATA_LANE1_IO_LOC Data Lane1 Value based on part selected.
DATA_LANE2_IO_LOC Data Lane2 Value based on part selected.
DATA_LANE3_IO_LOC Data Lane 3 Value based on part selected.
C_EN_HS_OBUFTDS Infer OBUFTDS for 7Series HS outputs 0 Enable OBUFTDS for 7 series devices