Pin Assignment Tab for UltraScale+ - 3.0 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

Document ID
PG238
Release Date
2024-12-04
Version
3.0 English

The Pin Assignment tab page allows you to select pins. The subsystem pin assignment configuration screen is shown in the following figure.

Note: This tab is not available for 7 series device configurations.
Figure 1. Customization Screen - Pin Assignment
HP IO Bank Selection
Select the HP I/O bank for clock lane and data lane implementation.
Clock Lane
Select the LOC for clock lane. This selection determines the I/O byte group within the selected HP I/O bank.
Data Lane 0/1/2/3
Displays the Data lanes 0, 1, 2, and 3 LOC based on the clock lane selection.