Shared Logic Outside the Subsystem - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

The MMCMs and PLLs are outside this subsystem instance. Select Include Shared Logic in example design if:

  • This is the second MIPI DSI TX subsystem instance in a multi-subsystem design.
  • You only want to manage one customization of the MIPI DSI TX subsystem in your design.
  • You want direct access to the input clocks.

To fully use the MMCM and PLL, customize one MIPI DSI TX subsystem with shared logic in the subsystem and one with shared logic in the example design. You can connect the MMCM/PLL outputs from the first MIPI DSI TX Subsystem to the second subsystem. If you want fine control, you can select Include Shared Logic in example design and base your own logic on the shared logic produced in the example design.

The following figure shows the sharable resource connections from the MIPI DSI TX Subsystem with shared logic included (MIPI_DSI_SS_Master) to the instance of another MIPI DSI TX Subsystem without shared logic (MIPI_DSI_SS_Slave00 and MIPI_DSI_SS_Slave01).

A total of 24 MIPI DSI TX subsystems can be implemented in a single HP I/O bank assuming one TX clock lane and one TX data lane are configured per core.

Important: The master and slave cores should be configured with the same line rate when sharing clkoutphy.
Figure 1. Shared Logic in the Example Design