Register Space - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

This section details registers available in the MIPI DSI TX Subsystem. The address map is split into following regions:

  • MIPI DSI TX Controller core
  • MIPI D-PHY core

Each IP core is given an address space of 64K. Example offset addresses from the system base address when the MIPI D-PHY registers are enabled are shown in the following table. Registers are provided for informational and debug purposes. For more details, refer to the provided driver API for the supported control of the MIPI DSI TX Subsystem.

Table 1. Sub-Core Address Offsets
IP Cores Offset
MIPI DSI TX Controller 0x0_0000
MIPI D-PHY 0x1_0000