I/O Planning for Versal Adaptive SoCs - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

The MIPI DSI TX subsystem GUI do not have I/O Assignment tab for Versal Adaptive SoCs. Instead, you need to use consolidated I/O planning in the main Vivado IDE Planning that is nibble planner. You can select any I/O for the clock and data lanes for the selected XPIO bank.

Detailed steps on how to perform the Vivado IDE planning is detailed under section "I/O Planning for Versal Advanced IO Wizard” in the Advanced I/O Wizard LogiCORE IP Product Guide (PG320). While selecting I/Os in a bank across nibbles, ensure that the Inter-nibble, Inter-byte clock guidelines are followed. Refer to the Clocking section in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).