General Design Guidelines - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

The subsystem is designed to fit into a video pipe transmit path. The input to the subsystem must be connected to a AXI4-Stream source that generates the pixel data. The output of the subsystem is MIPI-compliant serial data. Based on the throughput requirement, the output PPI interface can be tuned using customization parameters available for the subsystem, for example, the number of lanes.

Important: Initialize all MIPI interfaces in the same HP IO Bank at the same time. For example, multiple DSI or D-PHY instances in a system. For more information on implementing multiple interfaces in the same HP I/O Bank, see UltraScale Architecture SelectIO Resources User Guide (UG571).

Because the MIPI protocol does not allow throttling on the output interface, the module connected to the input of this subsystem should have sufficient bandwidth to pump the pixel data at the required rate to prevent underflow or overflow. For this purpose, it is always recommended to use Frame buffer / VDMA to drive data to MIPI DSI TX Subsystem. All the MIPI-specific video timing is taken care of by the MIPI DSI TX Subsystem.

All horizontal timing parameters should be in terms of word count (WC). For the same resolution, these might vary based on the pixel type selected (for example, RGB888 versus RGB666). The WC value should adhere to the word count restriction defined by the DSI specification. For example, the RGB888 word count should be a multiple of three.

The values of the timing registers must arrive in terms of the DSI word count (WC) such that these DSI bytes would approximately take the same amount of time as the video event that took in the pixel clock domain.

All the vertical timing parameters should be in terms of the number of lines. MIPI DSI TX Subsystem do not define any video timing parameters on its own. It is the sync device (DSI Panel) timing parameters that are the starting point to arrive at the timing parameters of the source device (MIPI DSI TX Subsystem).

If used properly the driver API is created to control the programming of all required registers. See the driver API documentation or example design provided with PG232 for more details. The following table shows the applicable timing parameters based on the Video mode:

Table 1. Applicable Parameters Based on Video Mode
Timing Register Description Sync Events Sync Pulses Burst Mode
Timing Register-1 (0x50) HSA (WC) No Yes No
Timing Register-1 (0x50) BLLP (WC) No No Yes
Timing Register-2 (0x54) HACT (WC) Yes Yes Yes
Timing Register-2 (0x54) VACT (Lines) Yes Yes Yes
Timing Register-3 (0x58) HBP (WC) Yes Yes Yes
Timing Register-3 (0x58) HFP (WC) Yes Yes Yes
Timing Register-4 (0x5C) VSA (Lines) Yes Yes Yes
Timing Register-4 (0x5C) VBP (Lines) Yes Yes Yes
Timing Register-4 (0x5C) VFP (Lines) Yes Yes Yes
Timing Register- 5 (0x6C) VFP (Lines) Yes Yes Yes