Resets - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

DSI Transmitter Controller has one hard reset (s_axis_aresetn) and one register based reset (soft reset).

  • s_axis_aresetn: All the core logic blocks reset to power-on conditions, including registers.
  • The soft reset resets the Interrupt Status register (ISR) of the DSI TX Controller and does not affect the core processing.

The subsystem has one external reset port:

  • s_axis_aresetn: Active-Low reset for the subsystem blocks.

The duration of s_axis_aresetn should be a minimum of 40 dphy_clk_200M cycles to propagate the reset throughout the system.

The reset sequence is shown in the following figure.

Figure 1. Reset Sequence

The following figure summarizes all resets available to the MIPI DSI TX Subsystem and the components affected by them.

Table 1. Subsystem Components
Sub-core s_axis_aresetn
MIPI DSI TX Controller Connected to s_axi_aresetn core port
MIPI DPHY Inverted signal connected to core_rst port
AXI Crossbar Connected to aresetn port
Note: The effect of each reset (s_axis_aresetn) is determined by the ports of the sub-cores to which they are connected. See the individual sub-core product guides for the effect of each reset signal.