This register allows you to selectively enable each error/status bits in the Interrupt Status register to generate an interrupt at output port. An IER bit set to ‘0’ does not inhibit an interrupt condition from being captured, but is reported in the status register.
| Bits | Name | Reset Value | Access | Description |
|---|---|---|---|---|
| 31 | Reserved | NA | NA | Reserved |
| 2 | Command Queue FIFO Full | 0x0 | R/W | Generate interrupt on command queue FIFO full condition. |
| 1 |
Unsupported/ Reserved Data type |
0x0 | R/W | Generate interrupt on “Unsupported/ Reserved” data type detection. |
| 0 | Pixel data underrun | 0x0 | R/W | Generate interrupt on “Pixel data underrun” condition |