Clocking - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

Document ID

PG238

Release Date

2023-10-18

Version

2.3 English

The subsystem clocks are described in the following table. Clock frequencies should be selected to match the data rate selected on the PPI interface. As the PPI interface does not allow any throttling, the input video stream should have enough bandwidth to provide the pixel data.

Table 1. Subsystem Clocks
Clock Name	Description
s_axis_aclk^{1, 2}	Clock used by the subsystem to receive pixel stream on AXI4-Stream Interface.
dphy_clk_200M	See the MIPI D-PHY LogiCORE IP Product Guide (PG202) for information on this clock. The same 200 MHz clock is used by register interface (s_axi) of the subsystem to access registers of its sub-cores.
s_axis_aclk: The frequency of this clock should be greater than or equal to the minimum required frequency based on the resolution. For example, for 1080p@60 Hz, eight bits per pixel, the minimum required pixel frequency is 148.5 MHz. Therefore, the `s_axis_aclk` should be a minimum of 148.5 MHz or higher. Maximum video clock is 250 MHz for UltraScale+ devices and 175 MHz for 7 series devices. If required, higher throughput can be achieved by increasing the Pixels per clock option from Single to Dual or Quad.