The MIPI DSI TX Subsystem is tested for functionality, performance, and reliability using AMD evaluation platforms. The MIPI DSI TX Subsystem verification test suites for all possible modules are continuously being updated to increase test coverage across the range of possible parameters for each individual module.
A series of MIPI DSI TX Subsystem test scenarios are validated using the AMD development boards listed in the following table. These boards permit the prototyping of system designs where the MIPI DSI TX Subsystem processes different short/long packets received on serial lines.
| Target Family | Evaluation Board | Characterization Board |
|---|---|---|
| AMD Zynq™ UltraScale+™ MPSoC | ZCU102 | N/A |
7 series devices do not have a native MIPI IOB support. Target the HP bank and/or HR Bank I/O for MIPI IP implementation. For more information on MIPI IOB compliant solution and guidance, refer to D-PHY Solutions (XAPP894) .
The following table shows the Interoperability Testing:
| MIPI Display | Board/Device | Tested Configuration | Resolution |
|---|---|---|---|
| B101UAN01.7 | ZCU102/ xczu9eg-ffvb1156-2-e |
1000 Mbps 4 Lanes RGB888 Sync Events |
1920x1200 @60fps |
| B101UAN01.7 | VCK190 |
1000 Mbps 4 Lanes RGB888 Sync Events |
1920x1200 @60fps |