AXI4-Lite Interfaces - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

Read from a register that does not have all 0s as a default to verify that the interface is functional. See the following figure for a read timing diagram. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

  • The lite_aclk inputs are connected and toggling.
  • The interface is not being held in reset, and lite_aresetn is an active-Low reset.
  • The main subsystem clocks are toggling and the enables are also asserted.
  • If the simulation has been run, verify in simulation and/or a debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.
Figure 1. AXI4-Lite Timing