Ports - 2.3 English

Table 1. Port Descriptions
Signal Name	Direction	Description
UltraScale+ Shared Logic Outside Subsystem
mipi_phy_if	Output	DPHY interface.
txbyteclkhs_in	Input	High-speed transmit byte clock.
clkoutphy_in	Input	DPHY serial clock.
pll_lock_in	Input	PLL lock indication.
txclkesc_in	Input	Clock for escape mode operations.
system_rst_in	Input	An active-High system reset output to be used by the example design level logic.
UltraScale+ Shared Logic in the Subsystem
mipi_phy_if	Output	DPHY interface.
txbyteclkhs	Output	High-speed transmit byte clock.
clkoutphy_out	Output	DPHY serial clock.
pll_lock_out	Output	PLL lock indication.
txclkesc_out	Output	Clock for escape mode operations.
system_rst_out	Output	An active-High system reset output to be used by the example design level logic.
7 series Shared Logic Outside Subsystem
mipi_phy_if	Output	DPHY interface.
txbyteclkhs_in	Input	Input to DPHY and used to transmit high-speed data.
oserdes_clk_in	Input	Used to connect the CLK pin of TX clock lane OSERDES.
oserdes_clk90_in	Input	Used to connect the CLK pin of TX data lane OSERDES and should have 90 phase shift with oserdes_clk_in.
oserdes_clkdiv_in	Input	Used to connect the CLKDIV pin of TX clock lane OSERDES and should be generated from oserdes_clk_in as source.
txclkesc_in	Input	Clock used for escape mode operations.
system_rst_in	Input	System level reset.
7 series Shared Logic in Subsystem
mipi_phy_if	Output	DPHY interface.
txbyteclkhs	Output	Clock used to transmit high speed data.
oserdes_clk_out	Output	Used to connect the CLK pin of TX clock lane OSERDES.
oserdes_clk90_out	Output	Used to connect the CLK pin of TX data lane OSERDES. It has 90 phase shift relationship with oserdes_clk_out.
oserdes_clkdiv_out	Output	Used to connect the CLKDIV pin of TX clock lane OSERDES and generated from oserdes_clk_out as source.
mmcm_lock_out	Output	MMCM lock indication.
txclkesc_out	Output	Clock for escape mode operations.
Other Ports
system_rst_out	Output	An active-High system reset output to be used by the example design level logic.
dphy_clk_200M	Input	Fixed 200 MHz clock required for MIPI DPHY. The same clock is used by s_axi interface of the subsystem.
s_axis_aclk	Input	AXI4-Stream Video clock
s_axis_aresetn	Input	AXI reset. Active-Low (Same reset for lite & stream interface).
s_axi_*	-	AXI4-Lite Interface
s_axis_tready	Output	AXI4-Stream Interface
s_axis_tvalid	Input	AXI4-Stream Interface
s_axis_tlast	Input	AXI4-Stream Interface
s_axis_tdata	Input	AXI4-Stream Interface. Width of this port is dependent on pixel type and no.of pixels per beat
s_axis_tkeep	Input	Not used in the design.
s_axis_tuser	Input	AXI4-Stream Interface. TUSER[0] is used to map the Frame start signal of the AXI4-Stream Video Interface. The core does not use this signal, but generates Frame start packets based on timing registers programming.
System Interface
Interrupt	Output	System Interrupt output