Example Configuration 2 - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)
Document ID
PG238
Release Date
2024-12-04
Version
3.0 English

Consider an exemplary MIPI DSI Panel with the following specifications:

Table 1. MIPI DSI Panel Parameters
Parameter Value
MIPI Parameters
Line Rate 500 Mb/s
Data Type

Compressed data

1-byte or 8 bits
Video Mode Sync Pulses
Lanes 2
Timing Parameters
Horizontal Active 640 pixels
Horizontal Blanking 100 pixels
Vertical Active 480 lines
Vertical Blanking 15 lines
Frame Rate 60 fps
Clock Frequency 21.978 MHz

To generate the values and set timing registers, based on the above example configuration, do the following:

  1. HACT(WC) = Active pixels per line * Bits per pixel/8.
    = 640*8/8
= 640 (decimal) -> 0x280
VACT = Active lines per frame
= 480(decimal) -> 0x1E0
  2. Get total line-time in pixel clock.
    Pixel Frequency = 21.978 Mhz

Pixel clock period = 1000/21.978 = 45.5 ns Total pixel in one line = 640+100 = 740 Total line time = 740*45.5 = 33670 ns
  3. Calculate blanking time.
    Byte clock(PPI) frequency = Line-rate/8 = 500/8 = 62.5Mhz Byte clock period = 1000/62.5 = 16 ns

HACT Duration = Pixels* (Bytes per pixel) * Byte clk Period/ Lanes

= (640 * 1 * 16) /2

= 5120 ns

Blanking time = Line-time - HACT Duration

= 33670 - 5120

= 28550 ns

WC(Bytes) to meet "Blanking time" of 9680 ns

= Blanking time * Lanes / (Byte Period)

= 28550 * 2 / 16

= 3568
  4. Get timing parameter based on the Video mode.
    Video mode: Sync Pulses

One line is composed of HSS +HSA + HSE + HBP + HACT + HFP HSS/HSE -> Short packet -> 4 bytes

HSA/HBP/HACT/HFP -> Long packet -> 4 bytes header + Payload + 2 bytes CRC Total of 2*4 + 4*6 = 32 bytes are covered in header and footer

Available blanking WC = 3568- 32 = 3536
  5. Divide the total available WC across available blanking parameters HSA, HBP, and HFP. Considering a ratio of 2:2:2 gives: (The values for HBP and HFP are the distribution of the horizontal blanking words across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Hence, consult the datasheet for your display.)
    Horizontal Sync Active (HSA) = 2*3536/6 = 1178 Horizontal Back Porch (HBP) = 2*3536/6 = 1178

Horizontal Front Porch (HFP) = 3536 - 1178 - 1178 = 
= 1180
  6. Set applicable horizontal timing registers with above calculated values.
    HSA = 1178(decimal) ' 0x49A HBP = 1178(decimal) ' 0x49A HFP = 1180(decimal) ' 0x49C
  7. Divide the total available vertical blanking lines between VSA, VBP, and VFP. Considering a ratio of 1:1:1 gives: (The values for VSA, VBP, and VFP are the distribution of the vertical blanking lines across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Hence, consult the data sheet for your display.)
    VSA = 5 (decimal) -> 0x05 VBP = 5 (decimal) -> 0x05 VFP = 5 (decimal) -> 0x05
  8. Final consolidate set of horizontal and vertical timing parameters for a DSI panel with 640x480@60 fps, 2-Lane, 500 Mb/s, Compressed data of 8-bit width, and Video clock of 21.978 MHz are as specified below:
    HACT = 0x280 HSA = 0x49A HBP = 0x49A HFP = 0x49C

VACT= 0x1E0 VSA = 0x05 VBP = 0x05 VFP = 0x05