Case 3: Disabling/Enabling the Core - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English
  1. Any time during the core operation, the core can be disabled using the core_config register.
  2. After the core is disabled, wait/poll until the control ready bit is set in the core_config register.
  3. Then you can re-enable the core after programming new settings.
Note: Any changes to bllp_mode and blanking packet type values during core operation take effect during the next BLLP period.
Figure 1. Core Programming Sequence - 2