Configuration Tab - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

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2.3 English

The Configuration tab page provides core related configuration parameters. The subsystem configuration screen is shown in the following figure.

Figure 1. Customization Screen - Configuration
DSI Lanes
Specifies the number of D-PHY lanes for this subsystem.
Input Pixels per beat
Specifies the number of pixels per clock received on AXI4-Stream Video interface.
DSI Data type
Specifies the Data Type (Pixel Format) as per DSI protocol (RGB888, RGB565, RGB666_L, RGB666_P, Compressed).
DCS Command Mode
Includes DCS command mode logic in controller sub core.
CRC Generation logic
Includes CRC generation logic for long packets.
Enable Initial Deskew Transmission
When set, the core generates initial skew calibration packets.
Note: Periodic Deskew is not supported.
Line Rate (Mbps)
Selects the line rate for the MIPI D-PHY core. AMD Vivado™ IDE automatically limits the line rates based on the selected device. For details about family or device-specific line rate support, refer to the datasheet for your device.

For 7 series devices, the internal IP timing is tested and validated up to a maximum value of 1152 Mbps (For example, On ZC702). Depending on the setup, meeting timing at higher line rates is possible. GUI provides an option to configure a higher line rate.

Note: Internal timing limitations are different than physical timing limitations, which are based on the PCB configuration and might be lower. The variables include external PHY, resistor network, and termination options. Ensure to validate the line requirement of design with full system handling.
LPX Period (ns)
Transmitted length of any low-power state period.
Enable AXI-4 Lite Register I/F
Select to enable the register interface for the MIPI D-PHY core.
Guarantees the clock Rising Edge Alignment to first payload bit on serial lines:
This option is available for AMD Versal™ TX configuration when selected the first payload bit is aligned to the rising edge of the serial clock.
Infer OBUFTDS for 7 series HS outputs
Select this option to infer OBUFTDS for HS outputs.
Note: This option is available only for 7 series D-PHY TX configuration. It is recommended to use this option for a D-PHY-compatible solution based on a resistive circuit. For details, see D-PHY Solutions (XAPP894) .