Revision History - 2.3 English

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

Document ID
Release Date
2.3 English

The following table shows the revision history for this document.

Section Revision Summary
10/18/2023 Version 2.3
Ports Updated the section.
10/19/2022 Version 2.3
Timing Register-5 Added Register 0x6C to support higher VFP values.
04/26/2022 Version 2.2
D-PHY LP HS Offset Added Register 0x68 to consider D-PHY LP to HS Switching latency.
07/15/2021 Version 2.2
N/A Editorial update.
07/14/2021 Version 2.2
Features Updated section
Configuration Tab Updated section with a new parameter
User Parameters Updated Table 1with C_EN_CTS_TX parameter
02/04/2021 Version 2.2
  • Updated Configuration Tab screen for V2.2.
  • Added information for Line Rate (Mbps).
  • Updated Default Line Rate (Mbps) value for DHY_LINERATE to 800.
  • Added Versal (VCK190) information in Interoperability.
  • Updated Licensing and Ordering.
  • Updated Application Software Development.
07/14/2020 Version 2.1
IP Facts Added support for AMD Versalâ„¢ devices.
06/26/2020 Version 2.1
  • New clocking architecture for line rates above 1500 Mbps, which removes need for ctrl_clk.
  • Relaxed restriction on input pixels per clock and data types for line rates above 1500 Mbps.
10/30/2019 Version 2.0
  • Extended line rate support to 2500 Mbps
  • Added DCS Long Packet Support
11/14/2018 Version 2.0
IP Facts Added Spartan 7 series support
Unsupported Features Added section
Shared Logic Outside the Subsystem Added an important note in the Shared Logic Outside the Subsystem section
Simulation Updated section
10/04/2017 Version 2.0
  • MIPI D-PHY serial pins grouped as interface
  • Board automation support added for FMC:LI-IMX274MIPI-FMC V1.0 which can be placed on ZCU102 FMC HPC0 slot. This FMC can interface MIPI AUO display.
04/05/2017 Version 1.1
N/A MIPI D-PHY 3.1 changes integrated
10/05/2016 Version 1.1
  • MIPI D-PHY 3.0 changes integrated
  • 7 series support
  • Details on Timing Register(s) calculation procedure and more than 4 Lane implementation added
04/06/2016 Version 1.0
Initial release. N/A