Tandem PROM UltraScale+ Example Tool Flow - 1.3 English

This section demonstrates the Vivado tool flow from start to finish when targeting an UltraScale+ device. Paths and pointers within this flow description assume the default component name pcie4_ultrascale_plus_0 is used.

1. Create a new Vivado project, and select a supported part/package shown in the previous table.
2. In the Vivado IP Core catalog, expand Standard Bus Interfaces > PCI Express , and double-click UltraScale+ PCI Express Integrated Block to open the Customize IP dialog box.
   Figure 1. Vivado IP Catalog
   
   
3. In the Customize IP dialog box Basic tab, ensure the following options are selected:
   • Mode: Advanced
   • PCIe Block Location: X1Y2
     Note: Use the required PCIe Block Location for the device targeted, as listed in the previous table. This design example targets a VU9P.
   • Tandem Configuration or Dynamic Function eXchange: Tandem PROM
     Figure 2. Tandem PROM
     
     
4. Perform additional PCIe customizations, and click OK to generate the core.
5. Click Generate when asked about which output products to create.
6. In the Sources tab, right-click the core, and select Open IP Example Design.

   A new instance of Vivado is created and the example design is automatically loaded into the Vivado IDE.

7. Run Synthesis and Implementation.

   Click Run Implementation in the Flow Navigator. Select OK to run through synthesis first. The design runs through the complete tool flow and the result is a fully routed design that supports Tandem PROM.

8. Set up PROM or Flash settings.

   Set the appropriate settings to correctly generate a bitstream for a PROM or flash memory device. In the PCIe core constraint file (for example, xilinx_pcie4_uscale_plus_x1y2.xdc):

   • Uncomment and customize any constraints that define the configuration settings.
   • The one constraint that is required is CONFIG_MODE. For example: set_property CONFIG_MODE BPI16 [current_design]

   For more information, see Programming the Device.

9. Generate the bitstream.

   After Synthesis and Implementation is complete, click Generate Bitstream in the Flow Navigator. A bitstream supporting Tandem configuration is generated in the runs directory, for example: ./pcie_ultrascale_plus_0_example.runs/impl/ xilinx_pcie4_uscale_plus_ep.bit.

   Note: You have the option of creating the first and stage 2 bitstreams independently. This flow allows you to control the loading of each stage through the JTAG interface for testing purposes. These bitstreams are the same as the ones used for the Tandem PCIe solution when loaded using JTAG. Attempting to load only the stage1 bitstream from flash memory does not work in hardware due to the difference in the HD.OVERRIDE_PERSIST setting that is used for Tandem PCIe designs.

   set_property HD.TANDEM_BITSTREAMS SEPARATE [current_design]

   The resulting bit files created are named xilinx_pcie4_uscale_plus_ep_tandem1.bit and xilinx_pcie4_uscale_plus_ep_tandem2.bit.

10. Generate the PROM file.

    Run the following command in the Vivado Tcl Console to create a PROM file supported on an AMD development board.

    write_cfgmem -format mcs -interface BPIx16 -size 256 -loadbit “up 0x0
    xilinx_pcie4_uscale_plus_ep.bit” xilinx_pcie3_uscale_ep.mcs