The example simulation design for the Endpoint configuration of the integrated block consists of two discrete parts:
- The Root Port Model, a test bench that generates, consumes, and checks PCI Express® bus traffic.
- The Programmed Input/Output (PIO) example design, a completer application for PCI Express. The PIO example design responds to Read and Write requests to its memory space and can be synthesized for testing in hardware.
Note:
Not all modes have example design support, for example, Straddle,
Address aligned mode, SRIOV, MSI-X, FLR, and MSI. The FLR for virtual functions is
not fully implemented in the example design; for this to work, you need to modify
the user logic.