Bitstream Generation - 1.3 English

The supplied scripts create bitstreams for any versions requested. The set runUpdateVerXBitstreams 1 flag (where X represents the version number) calls the bitstream generation routine later script. As seen in the "Running Bitstream Generation" section in the design_field_updates.tcl script, multiple values can be supplied to generate the different bitstream types, depending on what is needed. In most cases, and certainly for the streaming core, only TandemPCIe should be used. The following values generate these bitstreams (showing ver1 as an example):

TandemPCIe

Generates the following bitstreams.

• ver1_tpcie_tandem1 – stage 1 bitstream for Tandem PCIe, to be stored in flash.
• ver1_tpcie_tandem2 – stage 2 bitstream for Tandem PCIe, to be delivered over PCIe link; this bitstream is reloadable on the fly.

PR

Generates only this partial bitstream.

• ver1_tpcie_update_region_partial – partial bitstream to load in functionality of ver1.

Because stage 2 bitstreams can be used as partial bitstreams in the UltraScale+ Field Updates solution, there is no need to use this option for the AXI4 streaming core. For the DMA version of the core, the partial bit file will have a different size than the stage 2 bit file. The partial bit file does not include the DMA portion of the design (so it will not be reset during reconfiguration) but it does use expanded routing, which in some cases covers the entire device.

Ver1 does not have to be the version that is booted from flash. Rather, this version should be the most challenging design version available. The place and route results of this first version determine the partition pin locations, which locks the routing on the interface between the PCIe core and the user application.