The following figure illustrates the Dword-aligned transfer of a memory write TLP received from the link across the completer request interface. For the purpose of illustration, the starting Dword address of the data block being written into user memory is assumed to be (m*16 +3), for some integer m > 0. Its size is assumed to be n Dwords, for some n = k*16 - 1, where k > 1.
The transfer starts with the sixteen descriptor bytes, followed immediately by
the payload bytes. The signal m_axis_cq_tvalid remains asserted over
the duration of the packet. The user logic can prolong a beat at any time by pulling
down m_axis_cq_tready. The AXI4-Stream interface
signals m_axis_cq_tkeep (one bit per Dword position) indicate the valid Dwords in the
packet including the descriptor and any null bytes inserted between the descriptor and
the payload. That is, the m_axis_cq_tkeep bits are set to 1
contiguously from the first Dword of the descriptor until the last Dword of the payload.
During the transfer of a packet, the tkeep bits can be 0 only in
the last beat of the packet, when the packet does not fill the entire width of the
interface. The signal m_axis_cq_tlast is always asserted in the last
beat of the packet.
The completer request interface also includes the First Byte Enable and the
Last Enable bits in the m_axis_cq_tuser bus. These are activated in the
first beat of the packet, and provides information of the valid bytes in the first and
last Dwords of the payload.
The m_axi_cq_tuser bus also provides several optional signals
that can be used to simplify the logic associated with the user side of the interface,
or to support additional features. The signal is_sop is asserted in the
first beat of every packet, when its descriptor is on the bus. When the straddle option
is not in use, none of the other sop and eop indications within
m_axi_cq_tuser are relevant to the transfer of Requests. The byte
enable outputs byte_en[63:0] (one per byte lane) indicate the valid
bytes in the payload. These signals are asserted only when a valid payload byte is in
the corresponding lane (it is not asserted for descriptor or null bytes). The asserted
byte enable bits are always contiguous from the start of the payload, except when
payload size is two Dwords or less. For writes of two Dwords or less, the 1s on
byte_en are not be contiguous.
Another special case is that of a zero-length memory write, when the core
transfers a one-Dword payload with the byte_en bits all set to 0. Thus,
the user logic can, in all cases, use the byte_en
signals directly to enable the writing of the associated bytes into memory.
In the Dword-aligned mode, there can be a gap of zero, one, two, or three byte positions
between the end of the descriptor and the first payload byte, based on the address of
the first valid byte of the payload. The actual position of the first valid byte in the
payload can be determined either from first_be[3:0] or
byte_en[63:0] in the m_axis_cq_tuser bus.
When a Transaction Processing Hint is present in the
received TLP, the core transfers the parameters associated with the hint (TPH Steering
Tag and Steering Tag Type) on signals within the m_axis_cq_tuser bus.
The timing diagram in the following figure illustrates the 128-bit address aligned transfer of a memory write TLP received from the link across the completer request interface. For the purpose of illustration, the starting Dword address of the data block being written into user memory is assumed to be (m*16 +3), for some integer m > 0. Its size is assumed to be n Dwords, for some n = k*16 - 1, k > 1.
In the address-aligned mode, the delivery of the payload always starts in the
second quarter (bits 255:128) of the first beat, following the descriptor in the first
quarter. The first Dword the payload can appear on any of the four Dword positions in
the second quarter, based on the address of the first valid Dword of the payload. The
keep outputs m_axis_cq_tkeep remain High in the gap
between the descriptor and the payload. The actual position of the first valid byte in
the payload can be determined either from the least significant bits of the address in
the descriptor or from the byte enable bits byte_en[63:0] in the m_axis_cq_tuser
bus.
For writes of two Dwords or less, the 1s on byte_en are not contiguous
from the start of the payload. In the case of a zero-length memory write, the core
transfers a one-Dword payload with the byte_en bits all set to 0 for
the payload bytes.
