Generating the Core - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)
Document ID
PG213
Release Date
2024-06-21
Version
1.3 English
To generate a core using the default values in the AMD Vivado™ IDE, follow these steps:
  1. Start the Vivado IP catalog.
  2. Select File > Project > New.
  3. Enter a project name and location, click Next. This example uses project_name.xpr and project_dir.
  4. In the New Project wizard pages, do not add sources, existing IP, or constraints.
  5. From the Part tab (below), select these filter options:
    • Family: AMD Kintex™ UltraScale+™
    • Device: xcku11p
    • Package: ffva1156
    • Speed Grade: -3
    Note: If an unsupported silicon device is selected, the core is grayed out (unavailable) in the list of cores.
  6. Select xcku11p-ffva1156-3-e from the list.
  7. In the final project summary page, click OK.
  8. In the Vivado IP catalog, expand Standard Bus Interfaces > PCI Express, and double-click UltraScale+ Devices Integrated Block for PCIe to display the Customize IP dialog box.
  9. In the Component Name field, enter a name for the core.
    Note: <component_name> is used in this example.
  10. From the Device/Port Type drop-down menu, select the appropriate device/port type of the core (Endpoint or Root Port).
  11. Click OK to generate the core using the default parameters.