Supported Clock Frequencies and Interface Widths - 1.3 English

Supported Clock Frequencies and Interface Widths - 1.3 English - PG213

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID

PG213

Release Date

2025-11-20

Version

1.3 English

Table 1. Clock Frequencies and Interface Widths Supported For Various Configurations
PCIe Link Speed Capability	PCIe Link Width Capability	PIPE Interface Data Widths (bits)	AXI4 Streaming Interface Data Width (bits)	pipe_clk Frequency (MHz)	core_clk Frequency (MHz)	user_clk2 Frequency (MHz) (axi4st)	user_clk Frequency (MHz) (cfg, axi4st)
Gen1	X1	16	64	125	250	62.5	62.5
		16	64	125	250	125	125
		16	64	125	250	250	250
	X2	16	64	125	250	62.5	62.5
		16	64	125	250	125	125
		16	64	125	250	250	250
	X4	16	64	125	250	125	125
	X4	16	64	125	250	250	250
	X8	16	64	125	250	250	250
	X8	16	128	125	250	125	125
	X16	16	128	125	250	250	250
Gen2	X1	16	64	125/250	250	62.5	62.5
		16	64	125/250	250	125	125
		16	64	125/250	250	250	250
	X2	16	64	125/250	250	125	125
	X2	16	64	125/250	250	250	250
	X4	16	64	125/250	250	250	250
	X4	16	128	125/250	250	125	125
	X8	16	128	125/250	250	250	250
	X8	16	256	125/250	250	125	125
	X16	16	256	125/250	250	250	250
Gen3	X1	16/32	64	125/250	250	125	125
	X1	16/32	64	125/250	250	250	250
	X2	16/32	64	125/250	250	250	250
	X2	16/32	128	125/250	250	125	125
	X4	16/32	128	125/250	250	250	250
	X4	16/32	256	125/250	250	125	125
	X8	16/32	256	125/250	250/500²	250	250
	X16	16/32	512	125/250	500	500	250
Gen4	X1	16/32/64	64	125/250	250	250	250
	X1	16/32/64	128	125/250	250	125	125
	X2	16/32/64	128	125/250	250	250	250
	X2	16/32/64	256	125/250	250	125	125
	X4	16/32/64	256	125/250	250	250	250
	X8	16/32/64	512	125/250	500	500	250
For Gen1/Gen2 speed, the pipe data width is 16. For Gen3 speed, the pipe data width is 32 and for Gen4 speed, it is 64. In Gen3 configuration, when in Gen1, the pipe data width switches to 16. Similarly, the automatic switch happens in Gen4 based on the speed during the link training process. The pipe data width is not user configurable. For Gen3 x8 configuration, core_clk frequency is 250 MHz for -1L, -1LV, and -2LV speed grade devices. For Gen4 speed, pipe data width is effectively operating at 64-bit, however PCIe hard block pipe data width is operating at 32-bit. When pipe rate switches into Gen4 speed at speed change, PCIe pipe tx/rx data lanes [15:8] make up the upper 32-bit of PCIe pipe data, while PCIe pipe tx/rx data lanes [7:0] make up the lower 32-bit of PCIe pipe data, together they make up the full 64-bit pipe data width.