Follow these steps to build the Tandem IP and compile the sample design. The AMD Vivado™ Design Suite processes the design from IP customization to
bitstream generation for two design configurations.
- Launch the Customize IP dialog box to customize the UltraScale+
Devices Integrated Block for PCIe core.Note: This solution is supported only in version 1.3 (and newer) of the IP.
- Customize the PCIe IP core with Tandem PCIe with Field Updates selected. The Advanced Mode option must be selected to see this option.
- Generate output products by using the default Out of context per IP synthesis option. This synthesizes the IP to create a checkpoint that can be inserted in your full design.
- Right-click the IP in the Design Sources tab, and select Open IP Example Design.Important: The design, as delivered, must be processed in a scripted non-project mode, because the sample design's project is not yet enabled for DFX.
The example design comes with a set of scripts for use with the non-project Tcl flow.The sample scripts are located in the field_update_scripts folder, but these are all referenced by the master script in the design example folder. You can convert this example design to project mode, if needed.
- In a Vivado Tcl shell, source design_field_updates.tcl,
which is found in the project directory. This file compiles the example design
with two versions:
- With the default settings, Ver1 is the initial design so the static design (essentially just the PCIe IP) is used from this version.
- Ver2 is logically the same as Ver1 but shown as a separate configuration to give an example of what processing a second design revision looks like. In an actual user design, these logical modules would be replaced by different functionality.