|
Core Specifics |
| Supported Device Family
1
|
AMD
UltraScale+
|
| Supported User Interfaces |
AXI4-Stream
|
| Resources |
Performance and Resource Utilization
page
2
|
| Provided with Core
|
| Design Files |
Verilog |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Verilog |
| Supported S/W Driver
2
|
N/A |
| Tested Design Flows
3
|
| Design Entry |
Vivado Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 65751
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- The resource use data applies to both the
PCIE4 and PCIE4C blocks.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|