Other Bitstream Load Time Considerations - 1.3 English

Power-supply ramp times are design-dependent. Take care to not design in large ramp times or delays. The FPGA power supplies that must be provided to begin FPGA configuration are listed in UltraScale Architecture Configuration User Guide (UG570).

In many cases, the FPGA power supplies can ramp up simultaneously or even slightly before the system power supply. In these cases, the design gains timing margin because the 100 ms does not start counting until the system supplies are stable. Again, this is design-dependent. Systems should be characterized to determine the relationship between FPGA supplies and system supplies.

T_POR is 57 ms for standard power ramp rates, and 15 ms for fast ramp rates for UltraScale+ devices. See Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) and Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).

Consider two cases for Example 1 (Quad SPI flash [x4] operating at 66 MHz ± 200 ppm) from Calculating Bitstream Load Time for Tandem:

• Case 1: Without ATX Supply
• Case 2: With ATX Supply

Assume that the FPGA power supplies ramp to a stable level (2 ms) after the 3.3V and 12V system power supplies. This time difference is called T_{FPGA_PWR}. In this case, because the FPGA supplies ramp after the system supplies, the power supply ramp time takes away from the 100 ms margin.

The equations to test are:

T_POR + Bitstream Load Time + T_{FPGA_PWR} < 100 ms for non-ATX

T_POR + Bitstream Load Time + T_{FPGA_PWR} - 100 ms < 100 ms for ATX

Case 1: Without ATX Supply

Because there is no ATX supply, the 100 ms begins counting when the 3.3 V and 12 V system supplies reach within 9% and 8% of their nominal voltages, respectively (see the PCI Express Card Electromechanical Specification PCI-SIG Specifications (https://www.pcisig.com/specifications)).

50 ms (T_POR) + 42.7 ms (bitstream time) + 2 ms (ramp time) = 94.7 ms

94.7 ms < 100 ms PCIe standard (okay)

In this case, the margin is 5.3 ms.

Case 2: With ATX Supply

ATX supplies provide a PWR_OK signal that indicates when system power supplies are stable. This signal is asserted at least 100 ms after actual supplies are stable. Thus, this extra 100 ms can be added to the timing margin.

50 ms (T_POR) + 42.7 ms (bitstream time) + 2 ms (ramp time) - 100 ms = -5.3 ms

-5.3 ms < 100 ms PCIe standard (okay)

In this case, the margin is 105.3 ms.