The Configuration Status interface provides information on how the core is configured, such as the negotiated link width and speed, the power state of the core, and configuration errors. The following table defines the ports in the Configuration Status interface of the core.
| Port | I/O | Width | Description |
|---|---|---|---|
| cfg_phy_link_down | O | 1 | Configuration Link Down Status of the PCI Express link based on the Physical Layer LTSSM.
Note: Per the PCI Express Base Specification, rev.
3.0, LinkUp is 1b in the Recovery, L0, L0s, L1, and L2 cfg_ltssm
states. In the Configuration state, LinkUp can be 0b or 1b. It
is always 0b when the Configuration state is reached using
Detect > Polling > Configuration. LinkUp is 1b if the
configuration state is reached through any other state
transition.
Note: While reset is asserted, the output of this
signal are 0b until reset is released.
|
| cfg_phy_link_status | O | 2 | Configuration Link Status Status of the PCI Express link.
|
| cfg_negotiated_width | O | 3 | Negotiated Link Width This output indicates the negotiated width of the given PCI Express Link and is valid when cfg_phy_link_status[1:0] == 11b (DL Initialization is complete). Negotiated Link Width values:
|
| cfg_current_speed | O |
2 |
Current Link Speed This signal outputs the current link speed of the given PCI Express Link.
|
| cfg_max_payload | O | 2 | Max_Payload_Size This signal outputs the maximum payload size from Device Control register bits 7 down to 5. This field sets the maximum TLP payload size. As a Receiver, the logic must handle TLPs as large as the set value. As a Transmitter, the logic must not generate TLPs exceeding the set value.
|
| cfg_max_read_req | O | 3 | Max_Read_Request_Size This signal outputs the maximum read request size from Device Control register bits 14 down to 12. This field sets the maximum Read Request size for the logic as a Requester. The logic must not generate Read Requests with size exceeding the set value.
|
| cfg_function_status | O |
16 |
Configuration Function Status These outputs indicate the states of the Command register bits in the PCI configuration space of each function. These outputs are used to enable requests and completions from the host logic. The assignment of bits is as follows:
|
| cfg_vf_status | O | 504 |
Configuration Virtual Function Status
|
| cfg_function_power_state | O |
12 |
Configuration Function Power State These outputs indicate the current power state of the physical functions. Bits [2:0] capture the power state of function 0, and bits [5:3] capture that of function 1, and so on. The possible power states are:
|
| cfg_vf_power_state | O | 756 | Configuration Virtual Function Power State These outputs indicate the current power state of the virtual functions. Bits [2:0] capture the power state of virtual function 0, and bits [5:3] capture that of virtual function 1, and so on. The possible power states are:
|
| cfg_link_power_state | O | 2 | Current power state of the PCI Express link, and
is valid when cfg_phy_link_status[1:0] == 11b (DL Initialization is
complete).
|
| cfg_local_error_out | O | 5 | Local Error Conditions: Error priority is noted and priority 0 has
the highest priority.
Note: This signal might not work for all PCIe Link
Width/Speed configurations. Do not rely solely on this signal to
indicate an error. Alternatively, you can decode the AER
register to accurately detect errors.
|
| cfg_local_error_valid | O | 1 | Local Error Conditions Valid: Block activates this output for one
cycle when any of the errors in cfg_local_error_out[4:0] are
encountered. When driven 1b cfg_local_error_out[4:0] indicates local
error type. Priority of error reporting (for the case of concurrent
errors) is noted. Note: This signal might not
work for all PCIe Link Width/Speed configurations. Do not rely
solely on this signal to indicate an error. Alternatively, you
can decode AER register to accurately detect
errors.
|
| cfg_rx_pm_state | O | 2 | Current RX Active State Power Management L0s
State: Encoding is listed below and valid when cfg_ltssm_state is
indicating L0:
|
| cfg_tx_pm_state | O | 2 | Current TX Active State Power Management L0s
State: Encoding is listed below and valid when cfg_ltssm_state is
indicating L0:
|
| cfg_ltssm_state | O | 6 | LTSSM State. Shows the current LTSSM state:
|
| cfg_rcb_status | O |
4 |
RCB Status. Provides the setting of the Read Completion Boundary (RCB) bit in the Link Control register of each physical function. In Endpoint mode, bit 0 indicates the RCB for Physical Function 0 (PF 0), bit 1 indicates the RCB for PF 1, and so on. In RC mode, bit 0 indicates the RCB setting of the Link Control register of the RP, bit 1 is reserved. For each bit, a value of 0 indicates an RCB of 64 bytes and a value of 1 indicates 128 bytes. |
| cfg_dpa_substate_change | O | 4 | Dynamic Power Allocation Substate Change. In Endpoint mode, the core generates a one-cycle pulse on one of these outputs when a Configuration Write transaction writes into the Dynamic Power Allocation Control register to modify the DPA power state of the device. A pulse on bit 0 indicates such a DPA event for PF0 and a pulse on bit 1 indicates the same for PF1. The other 2 bits are reserved.These outputs are not active in Root Port mode. |
| cfg_obff_enable | O | 2 | Optimized Buffer Flush Fill Enable. This output reflects the setting of the OBFF Enable field in the Device Control 2 register.
|
| cfg_pl_status_change | O | 1 | This output is used by the core in Root Port
mode to signal one of the following link training-related events:
The pl_interrupt output is not active when the core is configured as an Endpoint. |
| cfg_tph_requester_enable | O | 4 | Bit 0 of this output reflect the setting of the TPH Requester Enable bit [8] of the TPH Requester Control register in the TPH Requester Capability Structure of physical function 0. Bit 1 corresponds to physical function 1. And so on for other physical functions. |
| cfg_tph_st_mode | O | 12 | Bits [2:0] of this output reflect the setting of the ST Mode Select bits in the TPH Requester Control register of physical function 0. Bits [5:3] reflect the setting of the same register field of PF 1. And so on for other physical functions. |
| cfg_vf_tph_requester_enable | O | 252 | Each bit of this output reflects the setting of the TPH Requester Enable bit 8 of the TPH Requester Control register in the TPH Requester Capability Structure of the corresponding virtual function. |
| cfg_vf_tph_st_mode | O | 756 | Bits [2:0] of this output reflect the setting of the ST Mode Select bits in the TPH Requester Control register of virtual function 0. Bits [5:3] reflect the setting of the same register field of VF 1, and so on. |
| pcie_tfc_nph_av | O | 4 | This output provides an indication of the
currently available header credit for Non-Posted TLPs on the
transmit side of the core. The user logic can check this output
before transmitting a Non-Posted request on the requester request
interface, to avoid blocking the interface when no credit is
available. The encodings are:
Because of pipeline delays, the value on this output can not include the credit consumed by the Non-Posted requests in the last eight cycles or less. The user logic must adjust the value on this output by the credit consumed by the Non-Posted requests it sent in the previous clock cycles, if any. |
| pcie_tfc_npd_av | O | 4 | This output provides an indication of the
currently available payload credit for Non-Posted TLPs on the
transmit side of the core. The user logic checks this output before
transmitting a Non-Posted request on the requester request
interface, to avoid blocking the interface when no credit is
available. The encodings are:
Because of pipeline delays, the value on this output does not include the credit consumed by the Non-Posted requests sent by the user logic in the last eight clock cycles or less. The user logic must adjust the value on this output by the credit consumed by the Non-Posted requests it sent in the previous clock cycles, if any. |
| pcie_rq_tag_av | O | 4 | This output provides an indication of the number
of free tags available for allocation to Non-Posted requests on the
PCIe master side of the core. The user logic checks this output
before transmitting a Non-Posted request on the requester request
interface, to avoid blocking the interface when no tags are
available. The encodings are:
Because of pipeline delays, the value on this output does not include the tags consumed by the Non-Posted requests sent by the user logic in the last 8 clock cycles or less. The user logic must adjust the value on this output by the number of Non-Posted requests it sent in the previous clock cycles, if any. |