Using Tandem PCIe on Zynq MPSoC Devices - 1.3 English

While the processing system (PS) and processor configuration access port (PCAP) are in control of the configuration logic, the programmable logic (PL) and the media configuration access port (MCAP) (as well as the internal configuration access port (ICAP)) are locked out of the configuration logic. By default, the PCAP is enabled and the MCAP does not have access to load Stage 2 until the PCAP_PR bit is switched.

The PCAP and MCAP/ICAP interfaces are mutually exclusive and cannot be used simultaneously. Switching between PCAP and MCAP/ICAP is possible, but you must ensure that no commands or data are being transmitted or received before changing interfaces. Failure to do this could lead to unexpected behavior. Bit 0 (PCAP_PR) of the Control Register (PCAP.CTRL) selects between MCAP/ICAP and PCAP for PL configuration. The default is PCAP (1), but that can be changed to MCAP/ICAP (0) to enable this configuration port. To enable the MCAP/ICAP for AMD Zynq™ UltraScale+™ MPSoC devices, set the PCAP_PR field of the pcap_ctrl (CSU) register. This bit selects between MCAP or ICAP, and PCAP for PL configuration. There are two ways to clear the PCAP_PR bit and grant the ICAP/MCAP access for loading a stage 2 image.

1. Write the PCAP_CTRL register to set MCAP/ICAP as configuration port through JTAG:
   • Use the AMD Vitis™ Xilinx Software Command-Line Tools (XSCT) to connect to the JTAG chain.
   • Select PSU as the target.
   • Use memory read (MRD) and memory write (MWR) to change the default behavior.
2. Write to the PCAP_CTRL register to set the MCAP/ICAP as the enabled configuration port through FSBL:
   • Place the logic under XFsbl_HookBeforeHandoff().

   A list of FSBL hooks can be found at https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/FSBL.

   //Command to SET ICAP as Configuration port//
   Xil_Out32(0xFFCA3008, 0x0); // write PCAP_CTRL