A memory read request is transferred across the completer request interface in
the same manner as a memory write request, except that the AXI4-Stream packet contains only the 16-byte descriptor. The following
figure illustrates the transfer of a memory read TLP received from the link across the
completer request interface. The packet is transferred in a single beat on the
interface. The signal m_axis_cq_tvalid remains asserted
over the duration of the packet. The user logic can prolong a beat by pulling down
m_axis_cq_tready. The signal is_sop in the m_axis_cq_tuser bus is
asserted when the first descriptor byte is on the bus.
The byte enable bits associated with the read request for the first and last Dwords are
supplied by the core on the sideband bus m_axis_cq_tuser. These bits
are valid when the descriptor is being transferred, and must be used by the user logic
to determine the byte-level starting address and the byte count associated with the
request. For the special cases of one-Dword and two-Dword reads, the byte enables can be
non-contiguous. The bye enables are contiguous in all other cases. A zero-length memory
read is sent on the completer request interface with the Dword count field in the
descriptor set to 1 and the first and last byte enables set to 0.
The user logic must respond to each memory read request with a Completion. The data requested by the read are be sent as a single Completion or multiple Split Completions. These Completions must be sent to the completer completion interface of the core. The Completions for two distinct requests are be sent in any order, but the Split Completions for the same request must be in order. The operation of the completer completion interface is described in 64/128/256-bit Completer Interface and 512-bit Completer Interface.