In a non-project environment, the same
basic approach as the project environment is used. First, create the IP using the IP
catalog as shown in the Tandem PCIe UltraScale+ Example Tool Flow. One of the results of core
generation is an .xci file, which is a listing of
all the core details. This file is used to regenerate all the required design
sources.
- Read in design sources, either the example design or your
design.
read_verilog <verilog_sources> read_vhdl <vhdl_sources> read_xdc <xdc_sources> - Define the target
device.
set_property PART <part> [current_project]Note: Even though this is a non-project flow, there is an implied project behind the scenes. This must be done to establish an explicit device before the IP is read in. - Read in the PCIe
IP.
read_ip pcie_ip_0.xci - Synthesize the design. This step generates the IP sources from the
.xci input. Note: When out of context synthesis is used, you might need to apply the Pblock constraints using a constraints file that is only applied during implementation. This is because some constraints depend on the entire design being combined to apply the constraints.
- Ensure that any customizations to the design, such as the identification of the configuration mode to set the persisted pins, are done in the design XDC file.
- Implement the
design.
opt_design place_design route_design - Generate the bit files. The
-bin_fileoption should be used for Tandem PCIe. The BIN file is aligned to a 32-bit boundary and can facilitate the software loading of the stage 2 bitstream over PCIe.write_bitstream -bin_file <file>.bit