Features - 1.3 English - PG213

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID
PG213
Release Date
2024-12-18
Version
1.3 English
  • PCIE4 block designed to comply with the PCI Express Base Specification, rev3.1 .
  • PCIE4C block designed to comply with the PCI Express Base Specification, rev3.1 and be compatible with the PCI Express Base Specification, rev4.0 .
    Note: PCIE4C block has feature limitations which limit the ability to be 4.0 compliant, refer to the Unsupported Features section for more details.
  • PCIE4CE block designed to comply with the PCI Express Base Specification, rev4.0 .
  • PCI Express® Endpoint, Legacy Endpoint, or Root Port Modes.
  • x1, x2, x4, x8, or x16 link widths with Gen1, Gen2, and Gen3 link speeds for PCIE4, PCIE4C, and PCIE4CE blocks.
  • x1, x2, x4, and x8 link widths with Gen4 link speeds for both PCIE4C and PCIE4CE blocks.
  • AXI4-Stream Interface to your logic.
  • AER (Advanced Error Reporting) and ECRC (End-to-End CRC) support.
  • Block RAM used for Transaction buffering.
  • One PCI Express virtual channel, and eight traffic classes.
  • Up to 4 physical functions and 252 virtual functions.
  • 3 x 64-bit, or 6 x 32-bit Base Address Registers (BARs) that are fully configurable.

For a full list of features, see Feature Summary.