The following PCI Express Base Specification 4.0 Version 1.0 features are not supported by PCIE4C (UltraScale+ HBM):
- Tag Scaling (10b Tag)
- Feature DLLP, Flow Control Scaling
- Retimer Present Bits
- Lane Margining
- Gen 4 compliance patterns for TX electrical pulse-width jitter (PWJ) test not supported
- Link Extension Devices (Retimers)
- Link Upconfigure Capability
Important: While the above limitations
limit the ability to be 4.0 compliant, interoperation at 16.0 GT/s speeds is
possible and works with the majority of 4.0 devices. Work with the vendor of the
connected PCIe device to ensure that these
limitations pose no issues. AMD conservatively
guides system designers and system integrators to use slots / topologies / links
which do not involve retimers where PCIE4C is used in systems designed to the PCI Express Base Specification Revision 4.0. AMD has not evaluated all possibilities of retimer
implementations and applications across the permissible range of link topologies,
link qualities, and link partners in system designs based on the PCI Express Base Specification Revision 4.0. This
guidance pertains to retimers specifically but not redrivers, as redrivers are
protocol-unaware.