Migrating from UltraScale to UltraScale+ Devices - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)
Document ID
PG213
Release Date
2024-06-21
Version
1.3 English

This section provides information for users migrating from the AMD UltraScale+™ devices Integrated Block for PCIe core to the AMD UltraScale™ devices Integrated Block for PCIe core.

New Ports

The following table lists the new ports in the UltraScale+ device core to the UltraScale device core.
Table 1. New Ports in the UltraScale+ Devices Core
Names I/O Notes
pcie_rq_seq_num0[5:0] O pcie_rq_seq_num in UltraScale
pcie_rq_seq_num_vld0 O pcie_rq_seq_num_vld in UltraScale
pcie_rq_tag0[7:0] O pcie_rq_tag in UltraScale
pcie_rq_tag_vld0 O pcie_rq_tag_vld in UltraScale
pcie_rq_seq_num1[5:0] O
pcie_rq_seq_num_vld1 O
pcie_rq_tag1[7:0] O
pcie_rq_tag_vld1 O
cfg_mgmt_function_number[7:0] I
cfg_mgmt_debug_access I
cfg_local_error_valid I
cfg_local_error_out[4:0] I
cfg_rx_pm_state[1:0] O
cfg_tx_pm_state[1:0] O
cfg_bus_number[7:0] O
cfg_dev_id_pf0[15:0] I IDs are user accessible through I/Os
cfg_dev_id_pf1[15:0] I
cfg_dev_id_pf2[15:0] I
cfg_dev_id_pf3[15:0] I
cfg_vend_id[15:0] I
cfg_rev_id_pf0[7:0] I
cfg_rev_id_pf1[7:0] I
cfg_rev_id_pf2[7:0] I
cfg_rev_id_pf3[7:0] I
cfg_subsys_id_pf0[15:0] I
cfg_subsys_id_pf1[15:0] I
cfg_subsys_id_pf2[15:0] I
cfg_subsys_id_pf3[15:0] I
cfg_vf_flr_func_num[7:0] I
cfg_interrupt_msi_pending_status_function_num[1:0] I
cfg_interrupt_msi_select[1:0] I
cfg_pm_aspm_l1_entry_reject I
cfg_pm_aspm_tx_l0s_entry_disable I
cfg_interrupt_msix_vec_pending[1:0] I
cfg_interrupt_msix_vec_pending_status O
pl_redo_eq I
pl_redo_eq_speed I
pl_eq_mismatch O
pl_redo_eq_pending O

Port Width Changes

The following table lists the ports for which widths were changed between the UltraScale devices core and the UltraScale+ devices core.

Table 2. Port Width Changes
Name I/O
pcie_rq_tag_av[3:0] O
pcie_tfc_nph_av[3:0] O
pcie_tfc_npd_av[3:0] O
pcie_cq_np_req[1:0] I
pcie_cq_np_req_count[5:0] O
cfg_mgmt_addr[9:0] I
cfg_negotiated_width[2:0] O
cfg_current_speed[1:0] O
cfg_max_payload[1:0] O
cfg_vf_status[503:0] O
cfg_vf_power_state[755:0] O
cfg_vf_tph_requester_enable[251:0] O
cfg_vf_tph_st_mode[755:0] O
cfg_vf_flr_in_process[251:0] O
cfg_vf_flr_runc_num[7:0] I
cfg_interrupt_msix_vf_enable[251:0] O
cfg_interrupt_msix_vf_mask[251:0] O
cfg_interrupt_msi_tph_st_tag[7:0] I
cfg_interrupt_msi_function_number[7:0] I

Deprecated Ports

The following table lists the ports that were deprecated in the UltraScale+ devices core relative to the UltraScale devices core.

Table 3. Ports Not Available in the UltraScale+ Devices Core
Name I/O
cfg_mgmt_type1_cfg_reg_access I
cfg_local_error O
cfg_ltr_enable O
cfg_dpa_substate_change[3:0] O
cfg_per_func_status_control[2:0] I
cfg_per_func_status_data[15:0] O
cfg_per_function_number[3:0] I
cfg_per_function_output_request I
cfg_per_function_update_done O
cfg_ds_function_number[2:0] I
cfg_interrupt_msi_vf_enable[7:0] O
cfg_interrupt_msix_sent O
cfg_interrupt_msix_fail O
user_tph_stt_address[4:0] I
user_tph_function_num[3:0] I
user_tph_stt_read_data[31:0] O
user_tph_stt_read_data_valid O
user_tph_stt_read_enable I
pl_eq_reset_eieos_count I

Dedicated PERST Routing

Dedicated reset routing is not used in the UltraScale+ core.