User Parameters - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID

PG046

Release Date

2023-10-19

Version

11.1 English

Table: Vivado IDE Parameter to User Parameter Relationship shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).

Table 4-1: Vivado IDE Parameter to User Parameter Relationship
Vivado IDE Parameter/Value⁽¹⁾	User Parameter/Value⁽¹⁾	Default Value
Core Options
Physical Layer
Lane Width (Bytes)	C_LANE_WIDTH	2
Line Rate (Gb/s)	C_LINE_RATE	3.125
Column Used	C_UCOLUMN_USED	right
Starting GT Quad	C_START_QUAD	Quad X0Y0
Starting GT Lane	C_START_Lane	X0Y0
GT Refclk Selection	C_REFCLK_SOURCE	MGTREFCLK0 of Quad X0Y0
GT Refclk (MHz)	C_REFCLK_FREQUENCY	125.000
INIT clk (MHz)	C_INIT_CLK	50.000
DRP clk (MHz)⁽⁴⁾	DRP_FREQ	50.000
Aurora without GT⁽⁵⁾	C_GTWIZ_OUT	false
Link Layer
Dataflow Mode	Dataflow_Config	Duplex
Interface	Interface_Mode	Framing
Flow Control	Flow_Mode	None
Back Channel	Backchannel_mode	Sidebands
Scrambler/Descrambler	C_USE_SCRAMBLER	false
Little Endian Support	C_USE_BYTESWAP	false
Error Detection
CRC	C_USE_CRC	false
Debug and Control
Vivado Lab Tools	C_USE_CHIPSCOPE	false
Additional transceiver control and status ports	TransceiverControl	false
GT Selections
Lanes	C_AURORA_LANES	1
Lane Assignment⁽²⁾⁽⁴⁾
Select transceiver to include GTXE2_CHANNEL_X0Y0 in your design	C_GT_LOC_1	1
Select transceiver to include GTXE2_CHANNEL_X0Y1 in your design	C_GT_LOC_2	X
Select transceiver to include GTXE2_CHANNEL_X0Y2 in your design	C_GT_LOC_3	X
Select transceiver to include GTXE2_CHANNEL_X0Y3 in your design	C_GT_LOC_4	X
Select transceiver to include GTXE2_CHANNEL_X0Y4 in your design	C_GT_LOC_5	X
Select transceiver to include GTXE2_CHANNEL_X0Y5 in your design	C_GT_LOC_6	X
Select transceiver to include GTXE2_CHANNEL_X0Y5 in your design	C_GT_LOC_7	X
Select transceiver to include GTXE2_CHANNEL_X0Y7 in your design	C_GT_LOC_8	X
Select transceiver to include GTXE2_CHANNEL_X0Y8 in your design	C_GT_LOC_9	X
Select transceiver to include GTXE2_CHANNEL_X0Y9 in your design	C_GT_LOC_10	X
Select transceiver to include GTXE2_CHANNEL_X0Y10 in your design	C_GT_LOC_11	X
Select transceiver to include GTXE2_CHANNEL_X0Y11 in your design	C_GT_LOC_12	X
Select transceiver to include GTXE2_CHANNEL_X0Y12 in your design	C_GT_LOC_13	X
Select transceiver to include GTXE2_CHANNEL_X0Y13 in your design	C_GT_LOC_14	X
Select transceiver to include GTXE2_CHANNEL_X0Y14 in your design	C_GT_LOC_15	X
Select transceiver to include GTXE2_CHANNEL_X0Y15 in your design	C_GT_LOC_16	X
GT Refclk (MHz)
GT Refclk1⁽⁴⁾	C_GT_CLOCK_1	GTXQ0
GT Refclk2⁽⁴⁾	C_GT_CLOCK_2	None
Shared Logic
Include Shared Logic in core⁽³⁾	SupportLevel	1
Include Shared Logic in example design (Default Mode)	SupportLevel	0
Single Ended INIT CLK	SINGLEEND_INITCLK	false
Single Ended GTREF CLK	SINGLEEND_GTREFCLK	false
Starting GT Quad	C_START_QUAD	Quad_X1Y0
Starting GT Lane	C_START_LANE	X1Y0
GT Refclk Selection	C_REFCLK_SOURCE	MGTREFCLK1 of Quad X1Y0
Notes: 1.Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter. 2.X0Y0 GT selection is based on column. 3.If Shared Logic in core option is selected, SupportLevel is 1. 4.Not available with UltraScale devices. 5.Generate Aurora without GT option is available only for UltraScale and UltraScale+ devices in IP catalog.