A 16-bit or 32-bit CRC, implemented for user data, is available in the <component name>_crc_top.v[hd] module. CRC16 is generated for 2-byte designs, and CRC32 is generated for 4-byte designs. The crc_valid and crc_pass_fail_n signals indicate the result of a received CRC with a transmitted CRC (see Table: CRC Module Ports). The CRC-CCITT (16'h1021) and the standard Ethernet polynomial (32'h04C11DB7) are used as CRC polynomials for 16-bit and 32-bit respectively. The CRC is computed per lane and is suffixed to the data. At the receiver AXI interface, the CRC is removed and the packet is sent as received at the AXI interface of the transmitter. This Figure illustrates how the same data packet is sent without CRC and when CRC option is enabled.
