The following figure shows a typical example of
streaming data. The Aurora 8B/10B core indicates that it is
ready to transfer data by asserting s_axi_tx_tready. One
cycle later, the user logic indicates that it is ready to transfer data by asserting the
s_axi_tx_tdata bus and the s_axi_tx_tvalid signal. Because both ready signals are now asserted, data D0 is
transferred from the user logic to the Aurora 8B/10B core.
Data D1 is transferred on the following clock cycle. In this example, the Aurora 8B/10B core deasserts its ready signal, s_axi_tx_tready, and no data is transferred until the next clock
cycle when, again, the s_axi_tx_tready signal is asserted.
Then the user logic deasserts s_axi_tx_tvalid on the next
clock cycle, and no data is transferred until both ready signals are asserted.
Figure 1. Typical Streaming Data Transfer
