Transceiver Interface - 11.1 English

IMPORTANT: The ports in the Transceiver Control And Status Interface must be driven in accordance with the appropriate GT user guide. Using the input signals listed in Table: Transceiver Ports improperly might result in unpredictable behavior of the IP core.

This interface includes the serial I/O ports of the transceivers, and the control and status.

Table 2-14: Transceiver Ports
Name	Direction	Clock Domain	Description
rxp[0:m–1]⁽¹⁾	Input	RX Serial Clock	Positive differential serial data input pin.
rxn[0:m–1]⁽¹⁾	Input	RX Serial Clock	Negative differential serial data input pin.
txp[0:m–1]⁽¹⁾	Output	TX Serial Clock	Positive differential serial data output pin.
txn[0:m–1]⁽¹⁾	Output	TX Serial Clock	Negative differential serial data output pin.
power_down	Input	user_clk	Drives the power-down input of the transceiver. For more information, see the applicable transceiver user guide.
loopback[2:0]	Input	user_clk	The loopback[2:0] port selects between the normal operation and different loopback modes of the transceiver. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 3].
tx_resetdone_out	Output	user_clk	The TXRESETDONE signal of the transceiver.
rx_resetdone_out	Output	user_clk	The RXRESETDONE signal of the transceiver.
tx_lock	Output	user_clk	Indicates that the incoming serial transceiver refclk is locked by the transceiver phase-locked loop (PLL). See the applicable transceiver guide for more information. Note: The tx_lock signal coming from the aurora is asynchronous. A synchronizer is added to use it in user_clk/init_clk domain. Update the clock domain column of tx_lock signal to async from the user_clk.
Transceiver DRP Ports
drpaddr_in/ gt<=: lane :>_drpaddr	Input	drpclk_in	DRP address bus.
drpclk_in/ gt<=: lane :>_drpclk	Input	drpclk_in	DRP interface clock.
drpdi_in/ gt<=: lane :>_drpdi	Input	drpclk_in	Data bus for writing configuration data from the FPGA logic resources to the transceiver.
drpdo_out/ gt<=: lane :>_drpdo	Output	drpclk_in	Data bus for reading configuration data from the transceiver to the FPGA logic resources.
drpen_in/ gt<=: lane :>_drpen	Input	drpclk_in	DRP enable signal.
drprdy_out/ gt<=: lane :>_drprdy	Output	drpclk_in	Indicates that the operation is complete for write operations and data is valid for read operations.
drpwe_in/ gt<=: lane :>_drpwe	Input	drpclk_in	DRP write enable.
Transceiver Debug Ports
gt<lane>_txpostcursor_in/ gt_txpostcursor⁽⁴⁾⁽⁶⁾	Input	async	Transmitter post-cursor TX pre-emphasis control.
gt<lane>_txprecursor_in/ gt_txprecursor⁽⁴⁾⁽⁶⁾	Input	async	Transmitter pre-cursor TX pre-emphasis control.
gt<lane>_txchardispmode_in⁽⁴⁾ ⁽⁶⁾⁽¹⁰⁾	Input	user_clk	Set High to work with txchardispval to force running disparity negative or positive when encoding TXDATA. Set Low to use normal running disparity.
gt<lane>_txchardispval_in⁽⁴⁾⁽⁶⁾ ⁽¹⁰⁾	Input	user_clk	Works with txchardispmode to provide running disparity control.
gt<lane>_txdiffctrl_in/ gt_txdiffctrl⁽⁴⁾⁽⁶⁾	Input	async	Driver Swing Control.
gt<lane>_txmaincursor_in⁽⁴⁾⁽⁶⁾ ⁽¹⁰⁾	Input	async	Allows the main cursor coefficients to be directly set if the TX_MAINCURSOR_SEL attribute is set to 1'b1.
gt<lane>_txpolarity_in/ gt_txpolarity⁽⁴⁾⁽⁶⁾	Input	user_clk	The txpolarity port is used to invert the polarity of outgoing data. •0: Not inverted. TXP is positive, and TXN is negative. •1: Inverted. TXP is negative, and TXN is positive.
gt<lane>_tx_buf_err_out⁽⁴⁾⁽⁶⁾⁽¹⁰⁾	Output	user_clk	TX buffer status. txbufstatus[1] is connected to this port.
gt<lane>_rxlpmhfhold_in⁽⁴⁾⁽⁷⁾⁽¹⁰⁾	Input	user_clk	When set to 1'b1, the current value of the high-frequency boost is held. When set to 1'b0, the high-frequency boost is adapted.
gt<lane>_rxlpmlfhold_in⁽⁴⁾⁽⁷⁾⁽¹⁰⁾	Input	user_clk	When set to 1'b1, the current value of the low-frequency boost is held. When set to 1'b0, the low-frequency boost is adapted.
gt<lane>_rxlpmen_in/ gt_rxlpmen⁽⁴⁾⁽⁸⁾	Input	async	RX datapath •0: decision feedback equalizer (DFE) •1: low power mode (LPM)
gt<lane>_rxcdrovrden_in/ gt_rxcdrovrden⁽⁴⁾⁽⁸⁾	Input	async	Reserved.
gt<lane>_rxcdrhold_in/ gt_rxcdrhold⁽⁴⁾⁽⁹⁾	Input	async	Hold the clock data recovery (CDR) control loop frozen.
gt<lane>_rxdfelpmreset_in/ gt_rxdfelpmreset⁽⁴⁾⁽⁸⁾	Input	async	This port is driven High and then deasserted to start the DFE reset process.
gt<lane>_rxmonitorout_out⁽⁴⁾⁽⁸⁾ ⁽¹⁰⁾	Output	async	GTX transceiver: •RXDFEVP[6:0] = RXMONITOROUT[6:0] •RXDFEUT[6:0] = RXMONITOROUT[6:0] •RXDFEAGC[4:0] = RXMONITOROUT[4:0] GTH transceiver: •RXDFEVP[6:0] = RXMONITOROUT[6:0] •RXDFEUT[6:0] = RXMONITOROUT[6:0] •RXDFEAGC[3:0] = RXMONITOROUT[4:1]
gt<lane>_rxmonitorsel_in⁽⁴⁾⁽⁸⁾ ⁽¹⁰⁾	Input	async	Select signal for rxmonitorout[6:0] •2'b00: Reserved •2'b01: Select automatic gain control (AGC) loop •2'b10: Select UT loop •2'b11: Select VP loop
gt<lane>_eyescanreset_in/ gt_eyescanreset⁽⁴⁾⁽⁹⁾	Input	async	This port is driven High and then deasserted to start the EYESCAN reset process.
gt<lane>_eyescandataerror_out/ gt_eyescandataerror⁽⁴⁾⁽⁹⁾	Output	async	Asserts High for one rec_clk cycle when an (unmasked) error occurs while in the COUNT or ARMED state.
gt<lane>_eyescantrigger_in/ gt_eyescantrigger⁽⁴⁾⁽⁹⁾	Input	user_clk	Causes a trigger event.
gt<lane>_rxbyteisaligned_out⁽⁴⁾ ⁽⁹⁾⁽¹⁰⁾	Output	user_clk	This signal from the comma detection and realignment circuit is High to indicate that the parallel data stream is properly aligned on byte boundaries according to comma detection. •0: Parallel data stream not aligned to byte boundaries •1: Parallel data stream aligned to byte boundaries
gt<lane>_rxcommadet_out/ gt_rxcommadet⁽⁴⁾⁽⁹⁾	Output	user_clk	This signal is asserted when the comma alignment block detects a comma. The assertion occurs several cycles before the comma is available at the FPGA RX interface. •0: Comma not detected •1: Comma detected
gt<lane>_rx_disp_err_out⁽⁴⁾⁽⁹⁾⁽¹⁰⁾	Output	user_clk	Indicates the corresponding byte shown on rxdata has a disparity error. The rxdisperr pin of the transceiver is connected to this port.
gt<lane>_rx_not_in_table_out⁽⁴⁾ ⁽⁹⁾⁽¹⁰⁾	Output	user_clk	Indicates the corresponding byte shown on rxdata was not a valid character in the 8B/10B table. rxnotintable pin of the transceiver is connected to this port.
gt<lane>_rx_realign_out⁽⁴⁾⁽⁹⁾⁽¹⁰⁾	Output	user_clk	This signal from the comma detection and realignment circuit indicates that the byte alignment within the serial data stream has changed due to comma detection. •0: Byte alignment has not changed •1: Byte alignment has changed Data can be lost or repeated when alignment occurs, which can cause data errors (and disparity errors when the 8B/10B decoder is used). The rxbyterealign pin of the transceiver is connected to this port.
gt<lane>_rx_buf_err_out⁽⁴⁾⁽⁹⁾⁽¹⁰⁾	Output	user_clk	RX buffer status. rxbufstatus[2] is connected to this port.
gt0_pll0lock_out, gt0_pll1lock_out⁽⁴⁾	Output	async	PLL0LOCK and PLL1LOCK of the 7 series FPGA GTP transceiver COMMON block. Available shared logic is in core.
gt1_pll0lock_out, gt1_pll1lock_out⁽⁴⁾	Output	async	PLL0LOCK and PLL1LOCK of the 7 series FPGA GTP transceiver COMMON block. Available shared logic is in the core and two quads are selected during core configuration.
gt<lane>_cplllock_out/ gt_cplllock⁽⁴⁾	Output	async	This active-High PLL frequency lock signal indicates that the PLL frequency is within predetermined tolerance. The transceiver and its clock outputs are not reliable until this condition is met. Not available with 7 series FPGAs GTP transceivers.
gt<lane>_txprbsforceerr_in/ gt_prbsforceerr⁽⁴⁾⁽⁶⁾	Input	async	When this port is driven High, errors are forced in the PRBS transmitter. While this port is asserted, the output data pattern contains errors. When txprbssel is set to 000, this port does not affect txdata.
gt<lane>_txprbssel_in/ gt_prbssel⁽⁴⁾⁽⁶⁾	Input	async	Transmitter pseudo-random binary sequence (PRBS) generator test pattern control.
gt<lane>_txpcsreset_in/ gt_txpcsreset⁽⁴⁾⁽⁶⁾	Input	async	This port is used to reset the TX PCS. It is driven High and then deasserted to start the PCS reset process. In sequential mode, activating this port only resets the TX PCS.
gt<lane>_txpmareset_in/ gt_txpmareset⁽⁴⁾⁽⁶⁾	Input	async	This port is used to reset the TX PMA. It is driven High and then deasserted to start the TX PMA reset process. In sequential mode, activating this port resets both the TX PMA and the TX PCS.
gt<lane>_txresetdone_out/ gt_txresetdone⁽⁴⁾⁽⁶⁾	Output	async	This active-High signal indicates the GTX or GTH transceiver TX has finished reset and is ready for use. This port is driven Low when gttxreset goes High and is not driven High until the GTX/GTH transceiver TX detects txuserrdy High.
gt<lane>_txbufstatus_out/ gt_txbufstatus⁽⁴⁾⁽⁶⁾	Output	user_clk	TX buffer status.
gt<lane>_txinhibit_in/ gt_txinhibit⁽⁴⁾⁽⁵⁾⁽¹⁰⁾⁽¹¹⁾	Input	user_clk	When High, this signal blocks transmission of TXDATA and forces the serial data output pin TXP TXP to 0 and TXN to 1.
gt<lane>_rxresetdone_out/ gt_rxresetdone⁽⁴⁾⁽⁹⁾	Output	user_clk	When asserted, this active-High signal indicates the GTX or GTH transceiver RX has finished reset and is ready for use. In sequential mode, this port is driven Low when gtrxreset is driven High. This signal is not driven High until rxuserrdy goes High. In single mode, this port is driven Low when any of the RX resets are asserted. This signal is not asserted until all RX resets are deasserted and rxuserrdy is asserted.
gt<lane>_rxbufstatus_out/ gt_rxbufstatus⁽⁴⁾⁽⁹⁾	Output	user_clk	RX buffer status.
gt<lane>_rxlpmhfovrden_in⁽⁴⁾⁽⁷⁾	Input	user_clk	When set to 1'b1, the high-frequency boost is controlled by the RXLPM_HF_CFG attribute. When set to 1'b0, the high-frequency boost is controlled by the rxlpmhfhold signal.
gt<lane>_rxlpmreset_in⁽⁴⁾⁽⁷⁾	Input	async	Resets the LPM circuitry.
gt<lane>_rxprbserr_out/ gt_rxprbserr⁽⁴⁾⁽⁹⁾	Output	user_clk	This non-sticky status output indicates that PRBS errors have occurred.
gt<lane>_rxprbssel_in/ gt_rxprbssel⁽⁴⁾⁽⁹⁾	Input	user_clk	Receiver PRBS checker test pattern control.
gt<lane>_rxpcsreset_in/ gt_rxpcsreset⁽⁴⁾⁽⁹⁾	Input	user_clk	This port is driven High and then deasserted to start the PCS reset process.
gt<lane>_rxpmareset_in/ gt_rxpmareset⁽⁴⁾⁽⁹⁾	Input	async	This port is driven High and then deasserted to start RX PMA reset process.
gt<lane>_rxpmaresetdone_out/ gt_rxpmaresetdone⁽⁴⁾	Output	async	This active-High signal indicates GTH/GTP RX PMA reset is complete. This port is driven Low when gtrxreset or rxpmareset is asserted. Available for duplex and RX-Only simplex configuration and applicable for 7 series GTP and GTH transceivers only.
gt<lane>_dmonitorout_out/ gt_dmonitorout⁽⁴⁾⁽⁹⁾	Output	async	Digital Monitor Output Bus
gt<lane>_rxbufreset_in/ gt_rxbufreset⁽⁴⁾⁽⁹⁾	Input	async	This port is driven High and then deasserted to start the RX elastic buffer reset process. In either single mode or sequential mode, activating rxbufreset resets the RX elastic buffer only.
gt_pcsrsvdin⁽⁴⁾⁽¹⁰⁾⁽¹¹⁾	Input	async	PCSRSVDIN[2] is the DRP reset pin. For read-only registers, if a DRPRDY is not seen within 500 DRPCLK cycles after initiating a DRP transaction, reset the DRP interface using the port PCSRSVDIN[2]. This is available only in UltraScale device based designs.
Notes: 1.m is the number of transceivers. 2.The transceiver debug ports are enabled if the Additional transceiver control and status ports check-box option is selected in the Vivado IDE. 3.<lane> takes values from 0 to AURORA_LANES. 4.For designs using UltraScale devices, the prefixes of the optional transceiver debug ports for single-lane cores are changed from gt<lane> to gt, and the postfixes _in and _out are removed. For multi-lane cores, the prefixes of the optional transceiver debug ports gt(n) are aggregated into a single port. 5.See the relevant transceiver user guide for more information on transceiver debug ports. 6.Available with duplex and TX-only simplex configurations. 7.Available with duplex and RX-only simplex configurations and applicable to 7 series FPGAs GTP transceivers only. 8.Available with duplex and RX-only simplex configurations and applicable to 7 series FPGAs GTX and GTH transceivers only. 9.Available with duplex and RX-only simplex configurations. 10.Not available with UltraScale devices. 11.Not available in 7 series devices. 12.Refer to the relevant UG transceiver guide for more information on DRP ports.